Merge branch 'clps711x/cleanup' into next/cleanup
* clps711x/cleanup: ARM: clps711x: Combine header files into one for clps711x-targets Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
985f03c2e9
7 changed files with 65 additions and 193 deletions
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@ -27,9 +27,11 @@
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#define PADR (0x0000)
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#define PBDR (0x0001)
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#define PCDR (0x0002)
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#define PDDR (0x0003)
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#define PADDR (0x0040)
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#define PBDDR (0x0041)
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#define PCDDR (0x0042)
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#define PDDDR (0x0043)
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#define PEDR (0x0080)
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#define PEDDR (0x00c0)
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@ -76,6 +78,18 @@
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#define SS2POP (0x16c0)
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#define KBDEOI (0x1700)
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#define DAIR (0x2000)
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#define DAIR0 (0x2040)
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#define DAIDR1 (0x2080)
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#define DAIDR2 (0x20c0)
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#define DAISR (0x2100)
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#define SYSCON3 (0x2200)
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#define INTSR3 (0x2240)
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#define INTMR3 (0x2280)
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#define LEDFLSH (0x22c0)
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#define SDCONF (0x2300)
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#define SDRFPR (0x2340)
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/* common bits: SYSCON1 / SYSCON2 */
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#define SYSCON_UARTEN (1 << 8)
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@ -172,4 +186,49 @@
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#define SYNCIO_SMCKEN (1 << 13)
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#define SYNCIO_TXFRMEN (1 << 14)
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#define DAIR_DAIEN (1 << 16)
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#define DAIR_ECS (1 << 17)
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#define DAIR_LCTM (1 << 19)
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#define DAIR_LCRM (1 << 20)
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#define DAIR_RCTM (1 << 21)
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#define DAIR_RCRM (1 << 22)
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#define DAIR_LBM (1 << 23)
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#define DAIDR2_FIFOEN (1 << 15)
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#define DAIDR2_FIFOLEFT (0x0d << 16)
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#define DAIDR2_FIFORIGHT (0x11 << 16)
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#define DAISR_RCTS (1 << 0)
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#define DAISR_RCRS (1 << 1)
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#define DAISR_LCTS (1 << 2)
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#define DAISR_LCRS (1 << 3)
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#define DAISR_RCTU (1 << 4)
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#define DAISR_RCRO (1 << 5)
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#define DAISR_LCTU (1 << 6)
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#define DAISR_LCRO (1 << 7)
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#define DAISR_RCNF (1 << 8)
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#define DAISR_RCNE (1 << 9)
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#define DAISR_LCNF (1 << 10)
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#define DAISR_LCNE (1 << 11)
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#define DAISR_FIFO (1 << 12)
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#define SYSCON3_ADCCON (1 << 0)
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#define SYSCON3_DAISEL (1 << 3)
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#define SYSCON3_ADCCKNSEN (1 << 4)
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#define SYSCON3_FASTWAKE (1 << 8)
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#define SYSCON3_DAIEN (1 << 9)
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#define SDCONF_ACTIVE (1 << 10)
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#define SDCONF_CLKCTL (1 << 9)
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#define SDCONF_WIDTH_4 (0 << 7)
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#define SDCONF_WIDTH_8 (1 << 7)
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#define SDCONF_WIDTH_16 (2 << 7)
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#define SDCONF_WIDTH_32 (3 << 7)
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#define SDCONF_SIZE_16 (0 << 5)
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#define SDCONF_SIZE_64 (1 << 5)
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#define SDCONF_SIZE_128 (2 << 5)
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#define SDCONF_SIZE_256 (3 << 5)
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#define SDCONF_CASLAT_2 (2)
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#define SDCONF_CASLAT_3 (3)
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#endif /* __ASM_HARDWARE_CLPS7111_H */
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@ -1,49 +0,0 @@
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/*
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* arch/arm/include/asm/hardware/cs89712.h
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*
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* This file contains the hardware definitions of the CS89712
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* additional internal registers.
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*
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* Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_HARDWARE_CS89712_H
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#define __ASM_HARDWARE_CS89712_H
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/*
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* CS89712 additional registers
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*/
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#define PCDR 0x0002 /* Port C Data register ---------------------------- */
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#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
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#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
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#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
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#define SDCONF_ACTIVE (1 << 10)
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#define SDCONF_CLKCTL (1 << 9)
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#define SDCONF_WIDTH_4 (0 << 7)
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#define SDCONF_WIDTH_8 (1 << 7)
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#define SDCONF_WIDTH_16 (2 << 7)
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#define SDCONF_WIDTH_32 (3 << 7)
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#define SDCONF_SIZE_16 (0 << 5)
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#define SDCONF_SIZE_64 (1 << 5)
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#define SDCONF_SIZE_128 (2 << 5)
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#define SDCONF_SIZE_256 (3 << 5)
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#define SDCONF_CASLAT_2 (2)
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#define SDCONF_CASLAT_3 (3)
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#endif /* __ASM_HARDWARE_CS89712_H */
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@ -1,31 +0,0 @@
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/*
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* arch/arm/include/asm/hardware/ep7211.h
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*
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* This file contains the hardware definitions of the EP7211 internal
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* registers.
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*
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* Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_HARDWARE_EP7211_H
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#define __ASM_HARDWARE_EP7211_H
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/*
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* XXX miket@bluemug.com: need to introduce EP7211 registers (those not
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* present in 7212) here.
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*/
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#endif /* __ASM_HARDWARE_EP7211_H */
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@ -1,71 +0,0 @@
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/*
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* arch/arm/include/asm/hardware/ep7212.h
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*
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* This file contains the hardware definitions of the EP7212 internal
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* registers.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_HARDWARE_EP7212_H
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#define __ASM_HARDWARE_EP7212_H
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/*
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* These registers are specific to the EP7212 only
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*/
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#define DAIR 0x2000
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#define DAIR0 0x2040
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#define DAIDR1 0x2080
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#define DAIDR2 0x20c0
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#define DAISR 0x2100
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#define SYSCON3 0x2200
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#define INTSR3 0x2240
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#define INTMR3 0x2280
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#define LEDFLSH 0x22c0
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#define DAIR_DAIEN (1 << 16)
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#define DAIR_ECS (1 << 17)
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#define DAIR_LCTM (1 << 19)
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#define DAIR_LCRM (1 << 20)
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#define DAIR_RCTM (1 << 21)
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#define DAIR_RCRM (1 << 22)
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#define DAIR_LBM (1 << 23)
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#define DAIDR2_FIFOEN (1 << 15)
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#define DAIDR2_FIFOLEFT (0x0d << 16)
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#define DAIDR2_FIFORIGHT (0x11 << 16)
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#define DAISR_RCTS (1 << 0)
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#define DAISR_RCRS (1 << 1)
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#define DAISR_LCTS (1 << 2)
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#define DAISR_LCRS (1 << 3)
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#define DAISR_RCTU (1 << 4)
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#define DAISR_RCRO (1 << 5)
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#define DAISR_LCTU (1 << 6)
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#define DAISR_LCRO (1 << 7)
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#define DAISR_RCNF (1 << 8)
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#define DAISR_RCNE (1 << 9)
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#define DAISR_LCNF (1 << 10)
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#define DAISR_LCNE (1 << 11)
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#define DAISR_FIFO (1 << 12)
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#define SYSCON3_ADCCON (1 << 0)
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#define SYSCON3_DAISEL (1 << 3)
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#define SYSCON3_ADCCKNSEN (1 << 4)
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#define SYSCON3_FASTWAKE (1 << 8)
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#define SYSCON3_DAIEN (1 << 9)
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#endif /* __ASM_HARDWARE_EP7212_H */
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@ -1,6 +1,6 @@
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if ARCH_CLPS711X
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menu "CLPS711X/EP721X Implementations"
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menu "CLPS711X/EP721X/EP731X Implementations"
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config ARCH_AUTCPU12
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bool "AUTCPU12"
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@ -45,26 +45,13 @@ config ARCH_P720T
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config ARCH_FORTUNET
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bool "FORTUNET"
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# XXX Maybe these should indicate register compatibility
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# instead of being mutually exclusive.
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config ARCH_EP7211
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bool
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depends on ARCH_EDB7211
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default y
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config ARCH_EP7212
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bool
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depends on ARCH_P720T || ARCH_CEIVA
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default y
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config EP72XX_ROM_BOOT
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bool "EP72xx ROM boot"
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depends on ARCH_EP7211 || ARCH_EP7212
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---help---
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bool "EP721x/EP731x ROM boot"
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help
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If you say Y here, your CLPS711x-based kernel will use the bootstrap
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mode memory map instead of the normal memory map.
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Processors derived from the Cirrus CLPS-711X core support two boot
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Processors derived from the Cirrus CLPS711X core support two boot
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modes. Normal mode boots from the external memory device at CS0.
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Bootstrap mode rearranges parts of the memory map, placing an
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internal 128 byte bootstrap ROM at CS0. This option performs the
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@ -61,32 +61,11 @@
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#define CS7_PHYS_BASE (0x00000000)
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#endif
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#if defined (CONFIG_ARCH_EP7211)
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#include <asm/hardware/ep7211.h>
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#elif defined (CONFIG_ARCH_EP7212)
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#include <asm/hardware/ep7212.h>
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#endif
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#define SYSPLD_VIRT_BASE 0xfe000000
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#define SYSPLD_BASE SYSPLD_VIRT_BASE
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#if defined (CONFIG_ARCH_AUTCPU12)
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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#endif
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#if defined (CONFIG_ARCH_CDB89712)
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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#define ETHER_START 0x20000000
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#define ETHER_SIZE 0x1000
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#define ETHER_BASE 0xfe000000
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@ -149,8 +128,6 @@
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#if defined (CONFIG_ARCH_CEIVA)
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#include <asm/hardware/ep7212.h>
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/*
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* The two flash banks are wired to chip selects 0 and 1. This is the mapping
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* for them.
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@ -211,8 +211,8 @@ config KINGSUN_DONGLE
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kingsun-sir.
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config EP7211_DONGLE
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tristate "EP7211 I/R support"
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depends on IRTTY_SIR && ARCH_EP7211 && IRDA && EXPERIMENTAL
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tristate "Cirrus Logic clps711x I/R support"
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depends on IRTTY_SIR && ARCH_CLPS711X && IRDA && EXPERIMENTAL
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help
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Say Y here if you want to build support for the Cirrus logic
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EP7211 chipset's infrared module.
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