OMAP4: DSS2: Register configuration changes for DSI
The following changes have changed from OMAP3 to OMAP4 DSI: -The register field DSI_PLL_FREQSEL in DSI_PLL_CONFIGURATION2 has been removed. -DCS_CMD_ENABLE and DCS_CMD_CODE bits have been moved from DSI_CTRL to DSI_VC_CTRLi, hence the control of the bits is available per VC. -DSI LDO powergood notification doesn't work on OMAP4. This is mentioned in OMAP4 errata revision 1.8(Errata 1.76). -OCP_WIDTH register field is included in DSI_VC_CTRL. -The SCP clock is also required to access DSI PLL registers Introduce dss features for these changes so that DSI runs on both OMAP3 and OMAP4. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Archit Taneja
Tomi Valkeinen
parent
2783fa849b
commit
9613c02b5f
3 changed files with 63 additions and 38 deletions
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@ -1275,7 +1275,7 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
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{
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int r = 0;
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u32 l;
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int f;
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int f = 0;
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u8 regn_start, regn_end, regm_start, regm_end;
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u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
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@ -1349,19 +1349,19 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
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dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
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BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
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if (cinfo->fint < 1000000)
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f = 0x3;
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else if (cinfo->fint < 1250000)
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f = 0x4;
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else if (cinfo->fint < 1500000)
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f = 0x5;
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else if (cinfo->fint < 1750000)
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f = 0x6;
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else
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f = 0x7;
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if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
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f = cinfo->fint < 1000000 ? 0x3 :
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cinfo->fint < 1250000 ? 0x4 :
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cinfo->fint < 1500000 ? 0x5 :
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cinfo->fint < 1750000 ? 0x6 :
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0x7;
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}
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l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
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l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
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if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
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l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
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l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
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11, 11); /* DSI_PLL_CLKSEL */
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l = FLD_MOD(l, cinfo->highfreq,
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@ -1877,9 +1877,6 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
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DSSDBG("dsi_complexio_init\n");
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/* CIO_CLK_ICG, enable L3 clk to CIO */
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REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
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/* A dummy read using the SCP interface to any DSIPHY register is
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* required after DSIPHY reset to complete the reset of the DSI complex
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* I/O. */
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@ -1904,10 +1901,12 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
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goto err;
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}
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if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
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DSSERR("ComplexIO LDO power down.\n");
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r = -ENODEV;
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goto err;
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if (dss_has_feature(FEAT_DSI_LDO_STATUS)) {
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if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
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DSSERR("ComplexIO LDO power down.\n");
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r = -ENODEV;
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goto err;
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}
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}
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dsi_complexio_timings();
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@ -2074,6 +2073,8 @@ static void dsi_vc_initial_config(int channel)
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r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
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r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
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r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
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if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
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r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
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r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
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r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
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@ -2098,6 +2099,10 @@ static int dsi_vc_config_l4(int channel)
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REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
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/* DCS_CMD_ENABLE */
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if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
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REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 30, 30);
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dsi_vc_enable(channel, 1);
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dsi.vc[channel].mode = DSI_VC_MODE_L4;
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@ -2122,6 +2127,10 @@ static int dsi_vc_config_vp(int channel)
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REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
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/* DCS_CMD_ENABLE */
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if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
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REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 30, 30);
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dsi_vc_enable(channel, 1);
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dsi.vc[channel].mode = DSI_VC_MODE_VP;
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@ -2777,8 +2786,11 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
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r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
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r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
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r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
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r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
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r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
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if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
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r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
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/* DCS_CMD_CODE, 1=start, 0=continue */
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r = FLD_MOD(r, 0, 25, 25);
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}
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dsi_write_reg(DSI_CTRL, r);
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@ -3375,6 +3387,10 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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{
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int r;
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/* The SCPClk is required for both PLL and CIO registers on OMAP4 */
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/* CIO_CLK_ICG, enable L3 clk to CIO */
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REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
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_dsi_print_reset_status();
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r = dsi_pll_init(dssdev, true, true);
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@ -3387,6 +3403,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
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dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
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dss_select_lcd_clk_source(dssdev->manager->id,
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DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
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DSSDBG("PLL OK\n");
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@ -252,7 +252,8 @@ static struct omap_dss_features omap3430_dss_features = {
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FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
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FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,
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FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
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FEAT_DSI_PLL_FREQSEL | FEAT_DSI_LDO_STATUS,
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.num_mgrs = 2,
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.num_ovls = 3,
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@ -271,7 +272,8 @@ static struct omap_dss_features omap3630_dss_features = {
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
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FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
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FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG,
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FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
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FEAT_DSI_PLL_FREQSEL |FEAT_DSI_LDO_STATUS,
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.num_mgrs = 2,
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.num_ovls = 3,
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@ -289,7 +291,8 @@ static struct omap_dss_features omap4_dss_features = {
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.has_feature =
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FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
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FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
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FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,
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FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
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FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH,
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.num_mgrs = 3,
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.num_ovls = 3,
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@ -26,22 +26,26 @@
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/* DSS has feature id */
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enum dss_feat_id {
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FEAT_GLOBAL_ALPHA = 1 << 0,
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FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
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FEAT_PRE_MULT_ALPHA = 1 << 2,
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FEAT_LCDENABLEPOL = 1 << 3,
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FEAT_LCDENABLESIGNAL = 1 << 4,
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FEAT_PCKFREEENABLE = 1 << 5,
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FEAT_FUNCGATED = 1 << 6,
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FEAT_MGR_LCD2 = 1 << 7,
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FEAT_LINEBUFFERSPLIT = 1 << 8,
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FEAT_ROWREPEATENABLE = 1 << 9,
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FEAT_RESIZECONF = 1 << 10,
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FEAT_GLOBAL_ALPHA = 1 << 0,
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FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
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FEAT_PRE_MULT_ALPHA = 1 << 2,
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FEAT_LCDENABLEPOL = 1 << 3,
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FEAT_LCDENABLESIGNAL = 1 << 4,
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FEAT_PCKFREEENABLE = 1 << 5,
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FEAT_FUNCGATED = 1 << 6,
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FEAT_MGR_LCD2 = 1 << 7,
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FEAT_LINEBUFFERSPLIT = 1 << 8,
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FEAT_ROWREPEATENABLE = 1 << 9,
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FEAT_RESIZECONF = 1 << 10,
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/* Independent core clk divider */
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FEAT_CORE_CLK_DIV = 1 << 11,
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FEAT_LCD_CLK_SRC = 1 << 12,
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FEAT_CORE_CLK_DIV = 1 << 11,
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FEAT_LCD_CLK_SRC = 1 << 12,
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/* DSI-PLL power command 0x3 is not working */
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FEAT_DSI_PLL_PWR_BUG = 1 << 13,
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FEAT_DSI_PLL_PWR_BUG = 1 << 13,
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FEAT_DSI_PLL_FREQSEL = 1 << 14,
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FEAT_DSI_LDO_STATUS = 1 << 15,
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FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 16,
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FEAT_DSI_VC_OCP_WIDTH = 1 << 17,
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};
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/* DSS register field id */
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