ARM: tegra30: create a DT header defining CLK IDs
Create a header file to define the clock IDs used by the Tegra30 clock binding. Remove the list of definitions from the binding documentation, and refer the reader to the header file. This will allow the same header to be used by both device tree files, and drivers implementing this binding, which guarantees that the two stay in sync. This also makes device trees more readable by using names instead of magic numbers. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, add header to clock/ instead of clk/ to match binding location] Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Hiroshi Doyu
Stephen Warren
parent
ec23ad67f6
commit
9513109df8
2 changed files with 269 additions and 207 deletions
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@ -12,212 +12,9 @@ Required properties :
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 160 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 cpu
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1 unassigned
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2 unassigned
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3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 gpio
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 unassigned
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 unassigned
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 i2s0
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31 cop_cache
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32 mc
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33 ahbdma
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34 apbdma
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35 unassigned
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36 kbc
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37 statmon
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38 pmc
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39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
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45 unassigned
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46 sbc3
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47 i2c5
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48 dsia
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49 unassigned (register bit affects cve and tvo)
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50 mipi
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51 hdmi
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52 csi
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53 tvdac
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54 i2c2
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55 uartc
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56 unassigned
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57 emc
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58 usb2
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59 usb3
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60 mpe
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61 vde
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62 bsea
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63 bsev
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64 speedo
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65 uartd
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66 uarte
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67 i2c3
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68 sbc4
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69 sdmmc3
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70 pcie
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71 owr
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72 afi
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73 csite
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74 pciex
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75 avpucq
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76 la
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77 unassigned
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78 unassigned
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79 dtv
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80 ndspeed
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81 i2cslow
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82 dsib
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83 unassigned
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84 irama
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85 iramb
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86 iramc
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87 iramd
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88 cram2
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89 unassigned
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90 audio_2x a/k/a audio_2x_sync_clk
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91 unassigned
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92 csus
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93 cdev2
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94 cdev1
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95 unassigned
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96 cpu_g
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97 cpu_lp
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98 3d2
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99 mselect
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100 tsensor
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101 i2s3
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102 i2s4
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103 i2c4
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104 sbc5
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105 sbc6
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106 d_audio
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107 apbif
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108 dam0
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109 dam1
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110 dam2
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111 hda2codec_2x
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112 atomics
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113 audio0_2x
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114 audio1_2x
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115 audio2_2x
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116 audio3_2x
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117 audio4_2x
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118 audio5_2x
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119 actmon
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120 extern1
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121 extern2
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122 extern3
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123 sata_oob
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124 sata
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125 hda
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127 se
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128 hda2hdmi
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129 sata_cold
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160 uartb
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161 vfir
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162 spdif_in
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163 spdif_out
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164 vi
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165 vi_sensor
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166 fuse
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167 fuse_burn
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168 cve
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169 tvo
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170 clk_32k
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171 clk_m
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172 clk_m_div2
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173 clk_m_div4
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174 pll_ref
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175 pll_c
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176 pll_c_out1
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177 pll_m
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178 pll_m_out1
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179 pll_p
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180 pll_p_out1
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181 pll_p_out2
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182 pll_p_out3
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183 pll_p_out4
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184 pll_a
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185 pll_a_out0
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186 pll_d
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187 pll_d_out0
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188 pll_d2
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189 pll_d2_out0
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190 pll_u
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191 pll_x
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192 pll_x_out0
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193 pll_e
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194 spdif_in_sync
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195 i2s0_sync
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196 i2s1_sync
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197 i2s2_sync
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198 i2s3_sync
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199 i2s4_sync
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200 vimclk
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201 audio0
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202 audio1
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203 audio2
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204 audio3
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205 audio4
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206 audio5
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207 clk_out_1 (extern1)
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208 clk_out_2 (extern2)
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209 clk_out_3 (extern3)
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210 sclk
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211 blink
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212 cclk_g
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213 cclk_lp
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214 twd
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215 cml0
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216 cml1
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217 hclk
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218 pclk
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In clock consumers, this cell represents the clock ID exposed by the
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CAR. The assignments may be found in header file
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<dt-bindings/clock/tegra30-car.h>.
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Example SoC include file:
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@ -229,7 +26,7 @@ Example SoC include file:
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};
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usb@c5004000 {
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clocks = <&tegra_car 58>; /* usb2 */
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clocks = <&tegra_car TEGRA30_CLK_USB2>;
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};
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};
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265
include/dt-bindings/clock/tegra30-car.h
Normal file
265
include/dt-bindings/clock/tegra30-car.h
Normal file
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@ -0,0 +1,265 @@
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/*
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* This header provides constants for binding nvidia,tegra30-car.
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*
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* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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* registers. These IDs often match those in the CAR's RST_DEVICES registers,
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* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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* this case, those clocks are assigned IDs above 160 in order to highlight
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* this issue. Implementations that interpret these clock IDs as bit values
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* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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* explicitly handle these special cases.
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*
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* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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* above.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
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#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
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#define TEGRA30_CLK_CPU 0
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/* 1 */
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/* 2 */
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/* 3 */
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#define TEGRA30_CLK_RTC 4
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#define TEGRA30_CLK_TIMER 5
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#define TEGRA30_CLK_UARTA 6
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/* 7 (register bit affects uartb and vfir) */
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#define TEGRA30_CLK_GPIO 8
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#define TEGRA30_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA30_CLK_I2S1 11
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#define TEGRA30_CLK_I2C1 12
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#define TEGRA30_CLK_NDFLASH 13
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#define TEGRA30_CLK_SDMMC1 14
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#define TEGRA30_CLK_SDMMC4 15
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/* 16 */
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#define TEGRA30_CLK_PWM 17
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#define TEGRA30_CLK_I2S2 18
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#define TEGRA30_CLK_EPP 19
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/* 20 (register bit affects vi and vi_sensor) */
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#define TEGRA30_CLK_GR2D 21
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#define TEGRA30_CLK_USBD 22
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#define TEGRA30_CLK_ISP 23
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#define TEGRA30_CLK_GR3D 24
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/* 25 */
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#define TEGRA30_CLK_DISP2 26
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#define TEGRA30_CLK_DISP1 27
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#define TEGRA30_CLK_HOST1X 28
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#define TEGRA30_CLK_VCP 29
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#define TEGRA30_CLK_I2S0 30
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#define TEGRA30_CLK_COP_CACHE 31
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#define TEGRA30_CLK_MC 32
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#define TEGRA30_CLK_AHBDMA 33
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#define TEGRA30_CLK_APBDMA 34
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/* 35 */
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#define TEGRA30_CLK_KBC 36
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#define TEGRA30_CLK_STATMON 37
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#define TEGRA30_CLK_PMC 38
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/* 39 (register bit affects fuse and fuse_burn) */
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#define TEGRA30_CLK_KFUSE 40
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#define TEGRA30_CLK_SBC1 41
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#define TEGRA30_CLK_NOR 42
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/* 43 */
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#define TEGRA30_CLK_SBC2 44
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/* 45 */
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#define TEGRA30_CLK_SBC3 46
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#define TEGRA30_CLK_I2C5 47
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#define TEGRA30_CLK_DSIA 48
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/* 49 (register bit affects cve and tvo) */
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#define TEGRA30_CLK_MIPI 50
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#define TEGRA30_CLK_HDMI 51
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#define TEGRA30_CLK_CSI 52
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#define TEGRA30_CLK_TVDAC 53
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#define TEGRA30_CLK_I2C2 54
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#define TEGRA30_CLK_UARTC 55
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/* 56 */
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#define TEGRA30_CLK_EMC 57
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#define TEGRA30_CLK_USB2 58
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#define TEGRA30_CLK_USB3 59
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#define TEGRA30_CLK_MPE 60
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#define TEGRA30_CLK_VDE 61
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#define TEGRA30_CLK_BSEA 62
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#define TEGRA30_CLK_BSEV 63
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#define TEGRA30_CLK_SPEEDO 64
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#define TEGRA30_CLK_UARTD 65
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#define TEGRA30_CLK_UARTE 66
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#define TEGRA30_CLK_I2C3 67
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#define TEGRA30_CLK_SBC4 68
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#define TEGRA30_CLK_SDMMC3 69
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#define TEGRA30_CLK_PCIE 70
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#define TEGRA30_CLK_OWR 71
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#define TEGRA30_CLK_AFI 72
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#define TEGRA30_CLK_CSITE 73
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#define TEGRA30_CLK_PCIEX 74
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#define TEGRA30_CLK_AVPUCQ 75
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#define TEGRA30_CLK_LA 76
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/* 77 */
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/* 78 */
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#define TEGRA30_CLK_DTV 79
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#define TEGRA30_CLK_NDSPEED 80
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#define TEGRA30_CLK_I2CSLOW 81
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#define TEGRA30_CLK_DSIB 82
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/* 83 */
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#define TEGRA30_CLK_IRAMA 84
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#define TEGRA30_CLK_IRAMB 85
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#define TEGRA30_CLK_IRAMC 86
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#define TEGRA30_CLK_IRAMD 87
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#define TEGRA30_CLK_CRAM2 88
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/* 89 */
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#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
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/* 91 */
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#define TEGRA30_CLK_CSUS 92
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#define TEGRA30_CLK_CDEV2 93
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#define TEGRA30_CLK_CDEV1 94
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/* 95 */
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#define TEGRA30_CLK_CPU_G 96
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#define TEGRA30_CLK_CPU_LP 97
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#define TEGRA30_CLK_GR3D2 98
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#define TEGRA30_CLK_MSELECT 99
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#define TEGRA30_CLK_TSENSOR 100
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#define TEGRA30_CLK_I2S3 101
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#define TEGRA30_CLK_I2S4 102
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#define TEGRA30_CLK_I2C4 103
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#define TEGRA30_CLK_SBC5 104
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#define TEGRA30_CLK_SBC6 105
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#define TEGRA30_CLK_D_AUDIO 106
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#define TEGRA30_CLK_APBIF 107
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#define TEGRA30_CLK_DAM0 108
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#define TEGRA30_CLK_DAM1 109
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#define TEGRA30_CLK_DAM2 110
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#define TEGRA30_CLK_HDA2CODEC_2X 111
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#define TEGRA30_CLK_ATOMICS 112
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#define TEGRA30_CLK_AUDIO0_2X 113
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#define TEGRA30_CLK_AUDIO1_2X 114
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#define TEGRA30_CLK_AUDIO2_2X 115
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#define TEGRA30_CLK_AUDIO3_2X 116
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#define TEGRA30_CLK_AUDIO4_2X 117
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#define TEGRA30_CLK_SPDIF_2X 118
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#define TEGRA30_CLK_ACTMON 119
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#define TEGRA30_CLK_EXTERN1 120
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#define TEGRA30_CLK_EXTERN2 121
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#define TEGRA30_CLK_EXTERN3 122
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#define TEGRA30_CLK_SATA_OOB 123
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#define TEGRA30_CLK_SATA 124
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#define TEGRA30_CLK_HDA 125
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/* 126 */
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#define TEGRA30_CLK_SE 127
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#define TEGRA30_CLK_HDA2HDMI 128
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#define TEGRA30_CLK_SATA_COLD 129
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/* 130 */
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/* 131 */
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/* 132 */
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/* 133 */
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/* 134 */
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/* 135 */
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/* 136 */
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/* 137 */
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/* 138 */
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/* 139 */
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/* 140 */
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/* 141 */
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/* 142 */
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/* 143 */
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/* 144 */
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/* 145 */
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/* 146 */
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/* 147 */
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/* 148 */
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/* 149 */
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/* 150 */
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/* 151 */
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/* 152 */
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/* 153 */
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/* 154 */
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/* 155 */
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/* 156 */
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/* 157 */
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/* 158 */
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/* 159 */
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#define TEGRA30_CLK_UARTB 160
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#define TEGRA30_CLK_VFIR 161
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#define TEGRA30_CLK_SPDIF_IN 162
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#define TEGRA30_CLK_SPDIF_OUT 163
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#define TEGRA30_CLK_VI 164
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#define TEGRA30_CLK_VI_SENSOR 165
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#define TEGRA30_CLK_FUSE 166
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#define TEGRA30_CLK_FUSE_BURN 167
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#define TEGRA30_CLK_CVE 168
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#define TEGRA30_CLK_TVO 169
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#define TEGRA30_CLK_CLK_32K 170
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#define TEGRA30_CLK_CLK_M 171
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#define TEGRA30_CLK_CLK_M_DIV2 172
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#define TEGRA30_CLK_CLK_M_DIV4 173
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#define TEGRA30_CLK_PLL_REF 174
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#define TEGRA30_CLK_PLL_C 175
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#define TEGRA30_CLK_PLL_C_OUT1 176
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#define TEGRA30_CLK_PLL_M 177
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#define TEGRA30_CLK_PLL_M_OUT1 178
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#define TEGRA30_CLK_PLL_P 179
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#define TEGRA30_CLK_PLL_P_OUT1 180
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#define TEGRA30_CLK_PLL_P_OUT2 181
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#define TEGRA30_CLK_PLL_P_OUT3 182
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#define TEGRA30_CLK_PLL_P_OUT4 183
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#define TEGRA30_CLK_PLL_A 184
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#define TEGRA30_CLK_PLL_A_OUT0 185
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#define TEGRA30_CLK_PLL_D 186
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#define TEGRA30_CLK_PLL_D_OUT0 187
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#define TEGRA30_CLK_PLL_D2 188
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#define TEGRA30_CLK_PLL_D2_OUT0 189
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#define TEGRA30_CLK_PLL_U 190
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#define TEGRA30_CLK_PLL_X 191
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#define TEGRA30_CLK_PLL_X_OUT0 192
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#define TEGRA30_CLK_PLL_E 193
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#define TEGRA30_CLK_SPDIF_IN_SYNC 194
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#define TEGRA30_CLK_I2S0_SYNC 195
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#define TEGRA30_CLK_I2S1_SYNC 196
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#define TEGRA30_CLK_I2S2_SYNC 197
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#define TEGRA30_CLK_I2S3_SYNC 198
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#define TEGRA30_CLK_I2S4_SYNC 199
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#define TEGRA30_CLK_VIMCLK_SYNC 200
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#define TEGRA30_CLK_AUDIO0 201
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#define TEGRA30_CLK_AUDIO1 202
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#define TEGRA30_CLK_AUDIO2 203
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#define TEGRA30_CLK_AUDIO3 204
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#define TEGRA30_CLK_AUDIO4 205
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#define TEGRA30_CLK_SPDIF 206
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#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
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#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
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#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
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#define TEGRA30_CLK_SCLK 210
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||||
#define TEGRA30_CLK_BLINK 211
|
||||
#define TEGRA30_CLK_CCLK_G 212
|
||||
#define TEGRA30_CLK_CCLK_LP 213
|
||||
#define TEGRA30_CLK_TWD 214
|
||||
#define TEGRA30_CLK_CML0 215
|
||||
#define TEGRA30_CLK_CML1 216
|
||||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
||||
/* 288 */
|
||||
/* 289 */
|
||||
/* 290 */
|
||||
/* 291 */
|
||||
/* 292 */
|
||||
/* 293 */
|
||||
/* 294 */
|
||||
/* 295 */
|
||||
/* 296 */
|
||||
/* 297 */
|
||||
/* 298 */
|
||||
/* 299 */
|
||||
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
|
||||
#define TEGRA30_CLK_CLK_MAX 301
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
|
||||
Loading…
Reference in a new issue