ARM: SoC non-critical fixes for 3.14
As usual, we have a batch of fixes that weren't considered significant enough to warrant going into the later -rcs for previous release, so they are queued up on this branch. A handful of these are for various DT fixups for Samsung platforms, and a handful of other minor things. There are also a couple of stable-marked patches for mvebu -- they came in quite late and we decided to keep them deferred until the first -stable release to get more coverage instead of squeezing them into 3.13. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJS4VfEAAoJEIwa5zzehBx3AhIP/RSEQSF66w6/BqYI8qJSFU0g c+4Ubb1i253ayc/bkY43CRVM1iZ9zOFw2O9chogGv6sNmYXOYgJ/R0PQQQyExduK vbi0O+t2rqv+TeD7p3vFyExe1+oppchfDkiS2dTGchWWjqYS2qQnCYjOT4kgC3TA zA2aBZ0oOtpa6OVPG1gAKPyHTwbzoXXkqs1PHpS1hyP0OBMYJl8yhfQfqqs0ZhdJ fHuYjDFnZnLJ8Mm9Ow9XzxzNEioSzYRAwWT/6BY2T6AWixrPTLDZD5RB8d5k5650 O8Od8DyxwHFTSgL+XR1iKaEqe6yd5vYwPmm74Iku/ZlqBQ+7XVEyFHFtOp4xyjy8 dpYho05qTPTkSSQVYC4XO+Vz3G9BPwY4aclUAKONkIYfVQYLWi87WLKjUDY17qVx 9mKAH0f0UP7d00BsVRsM3glSMk1666btySpjDQ8fVlGH9PK1/WiRPh+37q8X9I7I eslUuE3ykJa9i38Taxr+AN3rn0VnvlGEqkzjSDzq9oYERkoyqzYXyz1/SYM1/4kW f6Tc3aQemUeJc50jZ8nVNZja4n9I6ChxySP5JBh1qijlQRef475y8ADa0/mXivS2 Kez5DumlajsesiQTqiGY0CClMQajxbrZTVrfUkrr2UkCEX62YLHIB7TpZtepPYXn TrFoDWZ78CCCPOIC0M8m =QhN9 -----END PGP SIGNATURE----- Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-critical fixes from Olof Johansson: "As usual, we have a batch of fixes that weren't considered significant enough to warrant going into the later -rcs for previous release, so they are queued up on this branch. A handful of these are for various DT fixups for Samsung platforms, and a handful of other minor things. There are also a couple of stable-marked patches for mvebu -- they came in quite late and we decided to keep them deferred until the first -stable release to get more coverage instead of squeezing them into 3.13" * tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits) ARM: at91: smc: bug fix in sam9_smc_cs_read() i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board ARM: mvebu: Add support to get the ID and the revision of a SoC ARM: dts: msm: Fix gpio interrupt and reg length irqchip: sirf: set IRQ_LEVEL status_flags ARM: OMAP2+: gpmc: Move legacy GPMC width setting ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy() ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition ARM: OMAP2+: board-generic: update SoC compatibility strings Documentation: dt: OMAP: explicitly state SoC compatible strings ARM: OMAP2+: enable AM33xx SOC EVM audio ARM: OMAP2+: Select USB PHY for AM335x SoC ARM: bcm2835: Fix grammar in help message ARM: msm: trout: fix uninit var warning ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2 ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12 ARM: dts: add clock provider for mshc node for Exynos4412 SOC clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider ...
This commit is contained in:
Linus Torvalds
commit
93abdb7785
32 changed files with 384 additions and 82 deletions
|
|
@ -31,6 +31,59 @@ spinlock@1 {
|
|||
ti,hwmods = "spinlock";
|
||||
};
|
||||
|
||||
SoC Type (optional):
|
||||
|
||||
- General Purpose devices
|
||||
compatible = "ti,gp"
|
||||
- High Security devices
|
||||
compatible = "ti,hs"
|
||||
|
||||
SoC Families:
|
||||
|
||||
- OMAP2 generic - defaults to OMAP2420
|
||||
compatible = "ti,omap2"
|
||||
- OMAP3 generic - defaults to OMAP3430
|
||||
compatible = "ti,omap3"
|
||||
- OMAP4 generic - defaults to OMAP4430
|
||||
compatible = "ti,omap4"
|
||||
- OMAP5 generic - defaults to OMAP5430
|
||||
compatible = "ti,omap5"
|
||||
- DRA7 generic - defaults to DRA742
|
||||
compatible = "ti,dra7"
|
||||
- AM43x generic - defaults to AM4372
|
||||
compatible = "ti,am43"
|
||||
|
||||
SoCs:
|
||||
|
||||
- OMAP2420
|
||||
compatible = "ti,omap2420", "ti,omap2"
|
||||
- OMAP2430
|
||||
compatible = "ti,omap2430", "ti,omap2"
|
||||
|
||||
- OMAP3430
|
||||
compatible = "ti,omap3430", "ti,omap3"
|
||||
- AM3517
|
||||
compatible = "ti,am3517", "ti,omap3"
|
||||
- OMAP3630
|
||||
compatible = "ti,omap36xx", "ti,omap3"
|
||||
- AM33xx
|
||||
compatible = "ti,am33xx", "ti,omap3"
|
||||
|
||||
- OMAP4430
|
||||
compatible = "ti,omap4430", "ti,omap4"
|
||||
- OMAP4460
|
||||
compatible = "ti,omap4460", "ti,omap4"
|
||||
|
||||
- OMAP5430
|
||||
compatible = "ti,omap5430", "ti,omap5"
|
||||
- OMAP5432
|
||||
compatible = "ti,omap5432", "ti,omap5"
|
||||
|
||||
- DRA742
|
||||
compatible = "ti,dra7xx", "ti,dra7"
|
||||
|
||||
- AM4372
|
||||
compatible = "ti,am4372", "ti,am43"
|
||||
|
||||
Boards:
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,11 @@ Required properties :
|
|||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
|
||||
or "marvell,mv78230-i2c"
|
||||
or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
|
||||
Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
|
||||
initial version of the SoC which had broken offload
|
||||
support. Linux auto-detects this and sets it
|
||||
appropriately.
|
||||
- interrupts : The interrupt number
|
||||
|
||||
Optional properties :
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@
|
|||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing {
|
||||
clock-frequency = <50000>;
|
||||
clock-frequency = <47500000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <64>;
|
||||
|
|
|
|||
|
|
@ -38,9 +38,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@12550000 {
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&ldo20_reg &buck8_reg>;
|
||||
|
|
@ -49,7 +47,6 @@
|
|||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
|
|
|
|||
|
|
@ -122,9 +122,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@12550000 {
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
|
@ -132,7 +130,6 @@
|
|||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
|
|
@ -159,7 +156,7 @@
|
|||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing {
|
||||
clock-frequency = <50000>;
|
||||
clock-frequency = <47500000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <64>;
|
||||
|
|
|
|||
|
|
@ -442,13 +442,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
bus-width = <8>;
|
||||
mmc@12550000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
non-removable;
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
|
||||
pinctrl-names = "default";
|
||||
card-detect-delay = <200>;
|
||||
vmmc-supply = <&vemmc_reg>;
|
||||
clock-frequency = <400000000>;
|
||||
samsung,dw-mshc-ciu-div = <0>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
|
|
|
|||
|
|
@ -61,11 +61,4 @@
|
|||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
compatible = "samsung,exynos4412-dw-mshc";
|
||||
reg = <0x12550000 0x1000>;
|
||||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
pinctrl3 = &pinctrl_3;
|
||||
fimc-lite0 = &fimc_lite_0;
|
||||
fimc-lite1 = &fimc_lite_1;
|
||||
mshc0 = &mshc_0;
|
||||
};
|
||||
|
||||
pd_isp: isp-power-domain@10023CA0 {
|
||||
|
|
@ -176,4 +177,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
mshc_0: mmc@12550000 {
|
||||
compatible = "samsung,exynos4412-dw-mshc";
|
||||
reg = <0x12550000 0x1000>;
|
||||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fifo-depth = <0x80>;
|
||||
clocks = <&clock 301>, <&clock 149>;
|
||||
clock-names = "biu", "ciu";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -302,11 +302,13 @@
|
|||
buck7_reg: BUCK7 {
|
||||
regulator-name = "PVDD_BUCK7";
|
||||
regulator-always-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "PVDD_BUCK8";
|
||||
regulator-always-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <13>;
|
||||
google,needs-ghost-filter;
|
||||
linux,keymap = <0x0001003a /* CAPSLK */
|
||||
linux,keymap = <0x0001007d /* L_META */
|
||||
0x0002003b /* F1 */
|
||||
0x00030030 /* B */
|
||||
0x00040044 /* F10 */
|
||||
|
|
@ -130,6 +130,7 @@
|
|||
0x04060024 /* J */
|
||||
0x04080027 /* ; */
|
||||
0x04090026 /* L */
|
||||
0x040a002b /* \ */
|
||||
0x040b001c /* ENTER */
|
||||
|
||||
0x0501002c /* Z */
|
||||
|
|
|
|||
|
|
@ -60,11 +60,13 @@
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1700000000>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1700000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@
|
|||
samsung,pins = "gpx0-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@
|
|||
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
reg = <0x00800000 0x1000>;
|
||||
reg = <0x00800000 0x4000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <173>;
|
||||
interrupts = <0 32 0x4>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <150>;
|
||||
interrupts = <0 32 0x4>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
|
|
|
|||
|
|
@ -307,7 +307,7 @@
|
|||
clocks = <&i2c0_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ab3100: ab3100@0x48 {
|
||||
ab3100: ab3100@48 {
|
||||
compatible = "stericsson,ab3100";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&vica>;
|
||||
|
|
@ -385,10 +385,10 @@
|
|||
clocks = <&i2c1_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fwcam0: fwcam@0x10 {
|
||||
fwcam0: fwcam@10 {
|
||||
reg = <0x10>;
|
||||
};
|
||||
fwcam1: fwcam@0x5d {
|
||||
fwcam1: fwcam@5d {
|
||||
reg = <0x5d>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -208,6 +208,8 @@ CONFIG_SND_DEBUG=y
|
|||
CONFIG_SND_USB_AUDIO=m
|
||||
CONFIG_SND_SOC=m
|
||||
CONFIG_SND_OMAP_SOC=m
|
||||
CONFIG_SND_AM33XX_SOC_EVM=m
|
||||
CONFIG_SND_DAVINCI_SOC=m
|
||||
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
|
||||
CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
|
||||
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
|
||||
|
|
@ -222,6 +224,7 @@ CONFIG_USB_TEST=y
|
|||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_OMAP_USB2=y
|
||||
CONFIG_OMAP_USB3=y
|
||||
CONFIG_AM335X_PHY_USB=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG=y
|
||||
CONFIG_USB_GADGET_DEBUG_FILES=y
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ static void sam9_smc_cs_read(void __iomem *base,
|
|||
/* Pulse register */
|
||||
val = __raw_readl(base + AT91_SMC_PULSE);
|
||||
|
||||
config->nwe_setup = val & AT91_SMC_NWEPULSE;
|
||||
config->nwe_pulse = val & AT91_SMC_NWEPULSE;
|
||||
config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
|
||||
config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
|
||||
config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
|
||||
|
|
|
|||
|
|
@ -12,4 +12,4 @@ config ARCH_BCM2835
|
|||
select PINCTRL_BCM2835
|
||||
help
|
||||
This enables support for the Broadcom BCM2835 SoC. This SoC is
|
||||
use in the Raspberry Pi, and Roku 2 devices.
|
||||
used in the Raspberry Pi and Roku 2 devices.
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
|
@ -68,12 +69,11 @@ static void __init trout_init(void)
|
|||
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
rc = trout_init_mmc(system_rev);
|
||||
if (rc)
|
||||
printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc);
|
||||
#endif
|
||||
|
||||
if (IS_ENABLED(CONFIG_MMC)) {
|
||||
rc = trout_init_mmc(system_rev);
|
||||
if (rc)
|
||||
pr_crit("MMC init failure (%d)\n", rc);
|
||||
}
|
||||
}
|
||||
|
||||
static struct map_desc trout_io_desc[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
|
|||
|
||||
AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
|
||||
|
||||
obj-y += system-controller.o
|
||||
obj-y += system-controller.o mvebu-soc-id.o
|
||||
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
|
||||
obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/clocksource.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -28,6 +29,7 @@
|
|||
#include "armada-370-xp.h"
|
||||
#include "common.h"
|
||||
#include "coherency.h"
|
||||
#include "mvebu-soc-id.h"
|
||||
|
||||
static void __init armada_370_xp_map_io(void)
|
||||
{
|
||||
|
|
@ -45,8 +47,38 @@ static void __init armada_370_xp_timer_and_clk_init(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void __init i2c_quirk(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 dev, rev;
|
||||
|
||||
/*
|
||||
* Only revisons more recent than A0 support the offload
|
||||
* mechanism. We can exit only if we are sure that we can
|
||||
* get the SoC revision and it is more recent than A0.
|
||||
*/
|
||||
if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV)
|
||||
return;
|
||||
|
||||
for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
|
||||
struct property *new_compat;
|
||||
|
||||
new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
|
||||
|
||||
new_compat->name = kstrdup("compatible", GFP_KERNEL);
|
||||
new_compat->length = sizeof("marvell,mv78230-a0-i2c");
|
||||
new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
|
||||
GFP_KERNEL);
|
||||
|
||||
of_update_property(np, new_compat);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void __init armada_370_xp_dt_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
|
||||
i2c_quirk();
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
|
|
|||
119
arch/arm/mach-mvebu/mvebu-soc-id.c
Normal file
119
arch/arm/mach-mvebu/mvebu-soc-id.c
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* ID and revision information for mvebu SoCs
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* All the mvebu SoCs have information related to their variant and
|
||||
* revision that can be read from the PCI control register. This is
|
||||
* done before the PCI initialization to avoid any conflict. Once the
|
||||
* ID and revision are retrieved, the mapping is freed.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "mvebu-soc-id: " fmt
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include "mvebu-soc-id.h"
|
||||
|
||||
#define PCIE_DEV_ID_OFF 0x0
|
||||
#define PCIE_DEV_REV_OFF 0x8
|
||||
|
||||
#define SOC_ID_MASK 0xFFFF0000
|
||||
#define SOC_REV_MASK 0xFF
|
||||
|
||||
static u32 soc_dev_id;
|
||||
static u32 soc_rev;
|
||||
static bool is_id_valid;
|
||||
|
||||
static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
||||
{ .compatible = "marvell,armada-xp-pcie", },
|
||||
{ .compatible = "marvell,armada-370-pcie", },
|
||||
{},
|
||||
};
|
||||
|
||||
int mvebu_get_soc_id(u32 *dev, u32 *rev)
|
||||
{
|
||||
if (is_id_valid) {
|
||||
*dev = soc_dev_id;
|
||||
*rev = soc_rev;
|
||||
return 0;
|
||||
} else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int __init mvebu_soc_id_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int ret = 0;
|
||||
void __iomem *pci_base;
|
||||
struct clk *clk;
|
||||
struct device_node *child;
|
||||
|
||||
np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
|
||||
if (!np)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* ID and revision are available from any port, so we
|
||||
* just pick the first one
|
||||
*/
|
||||
child = of_get_next_child(np, NULL);
|
||||
if (child == NULL) {
|
||||
pr_err("cannot get pci node\n");
|
||||
ret = -ENOMEM;
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
clk = of_clk_get_by_name(child, NULL);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("cannot get clock\n");
|
||||
ret = -ENOMEM;
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
pr_err("cannot enable clock\n");
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
pci_base = of_iomap(child, 0);
|
||||
if (IS_ERR(pci_base)) {
|
||||
pr_err("cannot map registers\n");
|
||||
ret = -ENOMEM;
|
||||
goto res_ioremap;
|
||||
}
|
||||
|
||||
/* SoC ID */
|
||||
soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
|
||||
|
||||
/* SoC revision */
|
||||
soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
|
||||
|
||||
is_id_valid = true;
|
||||
|
||||
pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
|
||||
|
||||
iounmap(pci_base);
|
||||
|
||||
res_ioremap:
|
||||
clk_disable_unprepare(clk);
|
||||
|
||||
clk_err:
|
||||
of_node_put(child);
|
||||
of_node_put(np);
|
||||
|
||||
return ret;
|
||||
}
|
||||
core_initcall(mvebu_soc_id_init);
|
||||
|
||||
32
arch/arm/mach-mvebu/mvebu-soc-id.h
Normal file
32
arch/arm/mach-mvebu/mvebu-soc-id.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Marvell EBU SoC ID and revision definitions.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell Semiconductor
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MVEBU_SOC_ID_H
|
||||
#define __LINUX_MVEBU_SOC_ID_H
|
||||
|
||||
/* Armada XP ID */
|
||||
#define MV78230_DEV_ID 0x7823
|
||||
#define MV78260_DEV_ID 0x7826
|
||||
#define MV78460_DEV_ID 0x7846
|
||||
|
||||
/* Armada XP Revision */
|
||||
#define MV78XX0_A0_REV 0x1
|
||||
#define MV78XX0_B0_REV 0x2
|
||||
|
||||
#ifdef CONFIG_ARCH_MVEBU
|
||||
int mvebu_get_soc_id(u32 *dev, u32 *rev);
|
||||
#else
|
||||
static inline int mvebu_get_soc_id(u32 *dev, u32 *rev)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_MVEBU_SOC_ID_H */
|
||||
|
|
@ -78,6 +78,7 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static const char *omap3_boards_compat[] __initdata = {
|
||||
"ti,omap3430",
|
||||
"ti,omap3",
|
||||
NULL,
|
||||
};
|
||||
|
|
@ -173,6 +174,8 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
static const char *omap4_boards_compat[] __initdata = {
|
||||
"ti,omap4460",
|
||||
"ti,omap4430",
|
||||
"ti,omap4",
|
||||
NULL,
|
||||
};
|
||||
|
|
@ -193,6 +196,8 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_SOC_OMAP5
|
||||
static const char *omap5_boards_compat[] __initdata = {
|
||||
"ti,omap5432",
|
||||
"ti,omap5430",
|
||||
"ti,omap5",
|
||||
NULL,
|
||||
};
|
||||
|
|
@ -213,6 +218,7 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_SOC_AM43XX
|
||||
static const char *am43_boards_compat[] __initdata = {
|
||||
"ti,am4372",
|
||||
"ti,am43",
|
||||
NULL,
|
||||
};
|
||||
|
|
@ -230,6 +236,7 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_SOC_DRA7XX
|
||||
static const char *dra7xx_boards_compat[] __initdata = {
|
||||
"ti,dra7xx",
|
||||
"ti,dra7",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* This function will go away once the device-tree convertion is complete */
|
||||
static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
struct gpmc_settings *s)
|
||||
{
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (gpmc_nand_data->dev_ready) {
|
||||
s->wait_on_read = true;
|
||||
s->wait_on_write = true;
|
||||
}
|
||||
|
||||
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
|
||||
s->device_width = GPMC_DEVWIDTH_16BIT;
|
||||
else
|
||||
s->device_width = GPMC_DEVWIDTH_8BIT;
|
||||
}
|
||||
|
||||
int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
struct gpmc_timings *gpmc_t)
|
||||
{
|
||||
|
|
@ -98,33 +114,23 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
|||
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (gpmc_nand_data->of_node) {
|
||||
gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
|
||||
} else {
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (gpmc_nand_data->dev_ready) {
|
||||
s.wait_on_read = true;
|
||||
s.wait_on_write = true;
|
||||
}
|
||||
}
|
||||
|
||||
s.device_nand = true;
|
||||
|
||||
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
|
||||
s.device_width = GPMC_DEVWIDTH_16BIT;
|
||||
else
|
||||
s.device_width = GPMC_DEVWIDTH_8BIT;
|
||||
|
||||
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
err = gpmc_configure(GPMC_CONFIG_WP, 0);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
}
|
||||
|
||||
if (gpmc_nand_data->of_node)
|
||||
gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
|
||||
else
|
||||
gpmc_set_legacy(gpmc_nand_data, &s);
|
||||
|
||||
s.device_nand = true;
|
||||
|
||||
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
err = gpmc_configure(GPMC_CONFIG_WP, 0);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
|
||||
|
||||
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
|
||||
|
|
|
|||
|
|
@ -37,7 +37,9 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <linux/platform_data/mtd-nand-s3c2410.h>
|
||||
#include <linux/platform_data/mmc-sdhci-s3c.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <linux/platform_data/touchscreen-s3c2410.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
|
@ -215,6 +217,13 @@ static struct platform_device mini6410_lcd_powerdev = {
|
|||
.dev.platform_data = &mini6410_lcd_power_data,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
|
||||
.max_width = 4,
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S3C64XX_GPN(10),
|
||||
.ext_cd_gpio_invert = true,
|
||||
};
|
||||
|
||||
static struct platform_device *mini6410_devices[] __initdata = {
|
||||
&mini6410_device_eth,
|
||||
&s3c_device_hsmmc0,
|
||||
|
|
@ -322,6 +331,7 @@ static void __init mini6410_machine_init(void)
|
|||
|
||||
s3c_nand_set_platdata(&mini6410_nand_info);
|
||||
s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
|
||||
s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
|
||||
s3c24xx_ts_set_platdata(NULL);
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
|
|
|
|||
|
|
@ -69,9 +69,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
}
|
||||
regmap = syscon_node_to_regmap(syscon_np);
|
||||
if (!regmap) {
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_crit("U300: could not locate syscon regmap\n");
|
||||
return -ENODEV;
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
main_power_15 = regulator_get(&pdev->dev, "vana15");
|
||||
|
|
|
|||
|
|
@ -184,11 +184,13 @@
|
|||
#define U300_TIMER_APP_CRC (0x100)
|
||||
#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
|
||||
|
||||
#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
|
||||
#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
|
||||
|
||||
static void __iomem *u300_timer_base;
|
||||
|
||||
struct u300_clockevent_data {
|
||||
struct clock_event_device cevd;
|
||||
unsigned ticks_per_jiffy;
|
||||
};
|
||||
|
||||
/*
|
||||
* The u300_set_mode() function is always called first, if we
|
||||
* have oneshot timer active, the oneshot scheduling function
|
||||
|
|
@ -197,6 +199,9 @@ static void __iomem *u300_timer_base;
|
|||
static void u300_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
struct u300_clockevent_data *cevdata =
|
||||
container_of(evt, struct u300_clockevent_data, cevd);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
/* Disable interrupts on GPT1 */
|
||||
|
|
@ -209,7 +214,7 @@ static void u300_set_mode(enum clock_event_mode mode,
|
|||
* Set the periodic mode to a certain number of ticks per
|
||||
* jiffy.
|
||||
*/
|
||||
writel(TICKS_PER_JIFFY,
|
||||
writel(cevdata->ticks_per_jiffy,
|
||||
u300_timer_base + U300_TIMER_APP_GPT1TC);
|
||||
/*
|
||||
* Set continuous mode, so the timer keeps triggering
|
||||
|
|
@ -305,20 +310,23 @@ static int u300_set_next_event(unsigned long cycles,
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Use general purpose timer 1 as clock event */
|
||||
static struct clock_event_device clockevent_u300_1mhz = {
|
||||
.name = "GPT1",
|
||||
.rating = 300, /* Reasonably fast and accurate clock event */
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_next_event = u300_set_next_event,
|
||||
.set_mode = u300_set_mode,
|
||||
static struct u300_clockevent_data u300_clockevent_data = {
|
||||
/* Use general purpose timer 1 as clock event */
|
||||
.cevd = {
|
||||
.name = "GPT1",
|
||||
/* Reasonably fast and accurate clock event */
|
||||
.rating = 300,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC |
|
||||
CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_next_event = u300_set_next_event,
|
||||
.set_mode = u300_set_mode,
|
||||
},
|
||||
};
|
||||
|
||||
/* Clock event timer interrupt handler */
|
||||
static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_u300_1mhz;
|
||||
struct clock_event_device *evt = &u300_clockevent_data.cevd;
|
||||
/* ACK/Clear timer IRQ for the APP GPT1 Timer */
|
||||
|
||||
writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
|
||||
|
|
@ -379,6 +387,8 @@ static void __init u300_timer_init_of(struct device_node *np)
|
|||
clk_prepare_enable(clk);
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
|
||||
|
||||
setup_sched_clock(u300_read_sched_clock, 32, rate);
|
||||
|
||||
u300_delay_timer.read_current_timer = &u300_read_current_timer;
|
||||
|
|
@ -428,7 +438,7 @@ static void __init u300_timer_init_of(struct device_node *np)
|
|||
pr_err("timer: failed to initialize U300 clock source\n");
|
||||
|
||||
/* Configure and register the clockevent */
|
||||
clockevents_config_and_register(&clockevent_u300_1mhz, rate,
|
||||
clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
|
||||
1, 0xffffffff);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void)
|
|||
if (!(fifocon & S3C2410_UFCON_RESETBOTH))
|
||||
break;
|
||||
}
|
||||
|
||||
uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
|
||||
}
|
||||
}
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
|
|||
DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
|
||||
DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
|
||||
DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
|
||||
DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
|
||||
DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
|
||||
DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
|
||||
DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
|
||||
|
|
|
|||
|
|
@ -692,6 +692,7 @@ static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
|
|||
{ .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
|
||||
{ .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
|
||||
{ .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
|
||||
{ .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
|
||||
|
|
@ -783,6 +784,10 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
|
|||
drv_data->errata_delay = true;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
|
||||
drv_data->offload_enabled = false;
|
||||
drv_data->errata_delay = true;
|
||||
}
|
||||
out:
|
||||
return rc;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,9 +34,10 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
|
|||
struct irq_chip_type *ct;
|
||||
int ret;
|
||||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
unsigned int set = IRQ_LEVEL;
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
|
||||
handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
|
||||
handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
|
||||
|
||||
gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
|
||||
gc->reg_base = base;
|
||||
|
|
|
|||
Loading…
Reference in a new issue