watchdog: ImgTec PDC Watchdog Timer Driver
This commit adds support for ImgTec PowerDown Controller Watchdog Timer. Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Naidu Tellapati <Naidu.Tellapati@imgtec.com> Signed-off-by: Jude Abraham <Jude.Abraham@imgtec.com> [ezequiel: Minor style fixes] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Naidu Tellapati
Wim Van Sebroeck
parent
cc4f9c2a91
commit
93937669e9
3 changed files with 301 additions and 0 deletions
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@ -1235,6 +1235,17 @@ config BCM_KONA_WDT_DEBUG
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If in doubt, say 'N'.
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config IMGPDC_WDT
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tristate "Imagination Technologies PDC Watchdog Timer"
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depends on HAS_IOMEM
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depends on METAG || MIPS || COMPILE_TEST
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help
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Driver for Imagination Technologies PowerDown Controller
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Watchdog Timer.
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To compile this driver as a loadable module, choose M here.
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The module will be called imgpdc_wdt.
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config LANTIQ_WDT
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tristate "Lantiq SoC watchdog"
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depends on LANTIQ
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@ -142,6 +142,7 @@ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
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octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
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obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
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obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
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obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o
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# PARISC Architecture
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289
drivers/watchdog/imgpdc_wdt.c
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289
drivers/watchdog/imgpdc_wdt.c
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@ -0,0 +1,289 @@
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/*
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* Imagination Technologies PowerDown Controller Watchdog Timer.
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*
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* Copyright (c) 2014 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
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* 2012 Henrik Nordstrom
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/watchdog.h>
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/* registers */
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#define PDC_WDT_SOFT_RESET 0x00
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#define PDC_WDT_CONFIG 0x04
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#define PDC_WDT_CONFIG_ENABLE BIT(31)
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#define PDC_WDT_CONFIG_DELAY_MASK 0x1f
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#define PDC_WDT_TICKLE1 0x08
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#define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
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#define PDC_WDT_TICKLE2 0x0c
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#define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
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#define PDC_WDT_TICKLE_STATUS_MASK 0x7
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#define PDC_WDT_TICKLE_STATUS_SHIFT 0
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#define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
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#define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */
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#define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */
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#define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
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#define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
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/* Timeout values are in seconds */
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#define PDC_WDT_MIN_TIMEOUT 1
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#define PDC_WDT_DEF_TIMEOUT 64
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static int heartbeat;
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
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"(default = " __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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struct pdc_wdt_dev {
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struct watchdog_device wdt_dev;
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struct clk *wdt_clk;
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struct clk *sys_clk;
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void __iomem *base;
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};
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static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
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{
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struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
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writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
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writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
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return 0;
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}
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static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
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{
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unsigned int val;
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struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
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val = readl(wdt->base + PDC_WDT_CONFIG);
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val &= ~PDC_WDT_CONFIG_ENABLE;
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writel(val, wdt->base + PDC_WDT_CONFIG);
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/* Must tickle to finish the stop */
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pdc_wdt_keepalive(wdt_dev);
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return 0;
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}
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static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int new_timeout)
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{
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unsigned int val;
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struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
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wdt->wdt_dev.timeout = new_timeout;
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val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
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val |= order_base_2(new_timeout * clk_rate) - 1;
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writel(val, wdt->base + PDC_WDT_CONFIG);
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return 0;
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}
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/* Start the watchdog timer (delay should already be set) */
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static int pdc_wdt_start(struct watchdog_device *wdt_dev)
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{
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unsigned int val;
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struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
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val = readl(wdt->base + PDC_WDT_CONFIG);
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val |= PDC_WDT_CONFIG_ENABLE;
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writel(val, wdt->base + PDC_WDT_CONFIG);
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return 0;
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}
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static struct watchdog_info pdc_wdt_info = {
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.identity = "IMG PDC Watchdog",
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.options = WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops pdc_wdt_ops = {
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.owner = THIS_MODULE,
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.start = pdc_wdt_start,
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.stop = pdc_wdt_stop,
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.ping = pdc_wdt_keepalive,
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.set_timeout = pdc_wdt_set_timeout,
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};
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static int pdc_wdt_probe(struct platform_device *pdev)
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{
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int ret, val;
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unsigned long clk_rate;
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struct resource *res;
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struct pdc_wdt_dev *pdc_wdt;
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pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL);
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if (!pdc_wdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pdc_wdt->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pdc_wdt->base))
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return PTR_ERR(pdc_wdt->base);
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pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys");
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if (IS_ERR(pdc_wdt->sys_clk)) {
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dev_err(&pdev->dev, "failed to get the sys clock\n");
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return PTR_ERR(pdc_wdt->sys_clk);
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}
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pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt");
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if (IS_ERR(pdc_wdt->wdt_clk)) {
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dev_err(&pdev->dev, "failed to get the wdt clock\n");
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return PTR_ERR(pdc_wdt->wdt_clk);
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}
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ret = clk_prepare_enable(pdc_wdt->sys_clk);
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if (ret) {
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dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
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return ret;
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}
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ret = clk_prepare_enable(pdc_wdt->wdt_clk);
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if (ret) {
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dev_err(&pdev->dev, "could not prepare or enable wdt clock\n");
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goto disable_sys_clk;
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}
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/* We use the clock rate to calculate the max timeout */
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clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
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if (clk_rate == 0) {
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dev_err(&pdev->dev, "failed to get clock rate\n");
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ret = -EINVAL;
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goto disable_wdt_clk;
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}
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if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
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dev_err(&pdev->dev, "invalid clock rate\n");
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ret = -EINVAL;
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goto disable_wdt_clk;
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}
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if (order_base_2(clk_rate) == 0)
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pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
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else
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pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;
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pdc_wdt->wdt_dev.info = &pdc_wdt_info;
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pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;
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pdc_wdt->wdt_dev.max_timeout = 1 << PDC_WDT_CONFIG_DELAY_MASK;
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pdc_wdt->wdt_dev.parent = &pdev->dev;
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ret = watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev);
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if (ret < 0) {
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pdc_wdt->wdt_dev.timeout = pdc_wdt->wdt_dev.max_timeout;
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dev_warn(&pdev->dev,
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"Initial timeout out of range! setting max timeout\n");
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}
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pdc_wdt_stop(&pdc_wdt->wdt_dev);
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/* Find what caused the last reset */
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val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
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val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
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switch (val) {
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case PDC_WDT_TICKLE_STATUS_TICKLE:
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case PDC_WDT_TICKLE_STATUS_TIMEOUT:
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pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;
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dev_info(&pdev->dev,
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"watchdog module last reset due to timeout\n");
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break;
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case PDC_WDT_TICKLE_STATUS_HRESET:
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dev_info(&pdev->dev,
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"watchdog module last reset due to hard reset\n");
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break;
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case PDC_WDT_TICKLE_STATUS_SRESET:
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dev_info(&pdev->dev,
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"watchdog module last reset due to soft reset\n");
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break;
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case PDC_WDT_TICKLE_STATUS_USER:
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dev_info(&pdev->dev,
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"watchdog module last reset due to user reset\n");
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break;
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default:
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dev_info(&pdev->dev,
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"contains an illegal status code (%08x)\n", val);
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break;
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}
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watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
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platform_set_drvdata(pdev, pdc_wdt);
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watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);
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ret = watchdog_register_device(&pdc_wdt->wdt_dev);
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if (ret)
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goto disable_wdt_clk;
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return 0;
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disable_wdt_clk:
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clk_disable_unprepare(pdc_wdt->wdt_clk);
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disable_sys_clk:
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clk_disable_unprepare(pdc_wdt->sys_clk);
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return ret;
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}
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static void pdc_wdt_shutdown(struct platform_device *pdev)
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{
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struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
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pdc_wdt_stop(&pdc_wdt->wdt_dev);
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}
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static int pdc_wdt_remove(struct platform_device *pdev)
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{
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struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
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pdc_wdt_stop(&pdc_wdt->wdt_dev);
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watchdog_unregister_device(&pdc_wdt->wdt_dev);
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clk_disable_unprepare(pdc_wdt->wdt_clk);
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clk_disable_unprepare(pdc_wdt->sys_clk);
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return 0;
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}
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static const struct of_device_id pdc_wdt_match[] = {
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{ .compatible = "img,pdc-wdt" },
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{}
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};
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MODULE_DEVICE_TABLE(of, pdc_wdt_match);
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static struct platform_driver pdc_wdt_driver = {
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.driver = {
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.name = "imgpdc-wdt",
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.of_match_table = pdc_wdt_match,
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},
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.probe = pdc_wdt_probe,
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.remove = pdc_wdt_remove,
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.shutdown = pdc_wdt_shutdown,
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};
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module_platform_driver(pdc_wdt_driver);
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MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
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MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
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MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
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MODULE_LICENSE("GPL v2");
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