[MIPS] IP28: added cache barrier to assembly routines
IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
Ralf Baechle
parent
2064ba23e5
commit
930bff8822
4 changed files with 24 additions and 0 deletions
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@ -199,6 +199,7 @@ FEXPORT(__copy_user)
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*/
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#define rem t8
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R10KCBARRIER(0(ra))
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/*
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* The "issue break"s below are very approximate.
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* Issue delays for dcache fills will perturb the schedule, as will
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@ -231,6 +232,7 @@ both_aligned:
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PREF( 1, 3*32(dst) )
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.align 4
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1:
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R10KCBARRIER(0(ra))
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EXC( LOAD t0, UNIT(0)(src), l_exc)
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EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
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EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
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@ -272,6 +274,7 @@ EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
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EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
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SUB len, len, 4*NBYTES
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ADD src, src, 4*NBYTES
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R10KCBARRIER(0(ra))
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EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
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EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
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EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
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@ -287,6 +290,7 @@ less_than_4units:
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beq rem, len, copy_bytes
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nop
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1:
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R10KCBARRIER(0(ra))
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EXC( LOAD t0, 0(src), l_exc)
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ADD src, src, NBYTES
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SUB len, len, NBYTES
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@ -334,6 +338,7 @@ EXC( LDFIRST t3, FIRST(0)(src), l_exc)
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EXC( LDREST t3, REST(0)(src), l_exc_copy)
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SUB t2, t2, t1 # t2 = number of bytes copied
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xor match, t0, t1
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R10KCBARRIER(0(ra))
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EXC( STFIRST t3, FIRST(0)(dst), s_exc)
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beq len, t2, done
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SUB len, len, t2
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@ -354,6 +359,7 @@ src_unaligned_dst_aligned:
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* It's OK to load FIRST(N+1) before REST(N) because the two addresses
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* are to the same unit (unless src is aligned, but it's not).
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*/
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R10KCBARRIER(0(ra))
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EXC( LDFIRST t0, FIRST(0)(src), l_exc)
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EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
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SUB len, len, 4*NBYTES
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@ -384,6 +390,7 @@ cleanup_src_unaligned:
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beq rem, len, copy_bytes
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nop
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1:
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R10KCBARRIER(0(ra))
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EXC( LDFIRST t0, FIRST(0)(src), l_exc)
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EXC( LDREST t0, REST(0)(src), l_exc_copy)
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ADD src, src, NBYTES
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@ -399,6 +406,7 @@ copy_bytes_checklen:
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nop
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copy_bytes:
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/* 0 < len < NBYTES */
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R10KCBARRIER(0(ra))
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#define COPY_BYTE(N) \
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EXC( lb t0, N(src), l_exc); \
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SUB len, len, 1; \
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@ -528,6 +536,7 @@ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
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ADD a1, a2 # src = src + len
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r_end_bytes:
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R10KCBARRIER(0(ra))
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lb t0, -1(a1)
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SUB a2, a2, 0x1
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sb t0, -1(a0)
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@ -542,6 +551,7 @@ r_out:
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move a2, zero
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r_end_bytes_up:
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R10KCBARRIER(0(ra))
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lb t0, (a1)
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SUB a2, a2, 0x1
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sb t0, (a0)
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@ -86,6 +86,7 @@ FEXPORT(__bzero)
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.set at
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#endif
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */
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#endif
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@ -103,11 +104,13 @@ FEXPORT(__bzero)
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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1: PTR_ADDIU a0, 64
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R10KCBARRIER(0(ra))
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f_fill64 a0, -64, a1, fwd_fixup
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bne t1, a0, 1b
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.set noreorder
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memset_partial:
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R10KCBARRIER(0(ra))
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PTR_LA t1, 2f /* where to start */
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#if LONGSIZE == 4
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PTR_SUBU t1, t0
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@ -129,6 +132,7 @@ memset_partial:
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beqz a2, 1f
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PTR_ADDU a0, a2 /* What's left */
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), last_fixup)
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#endif
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@ -143,6 +147,7 @@ small_memset:
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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bne t1, a0, 1b
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sb a1, -1(a0)
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@ -38,6 +38,7 @@ FEXPORT(__strncpy_from_user_nocheck_asm)
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.set noreorder
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1: EX(lbu, t0, (v1), fault)
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PTR_ADDIU v1, 1
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R10KCBARRIER(0(ra))
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beqz t0, 2f
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sb t0, (a0)
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PTR_ADDIU v0, 1
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@ -398,4 +398,12 @@ symbol = value
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#define SSNOP sll zero, zero, 1
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#ifdef CONFIG_SGI_IP28
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/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
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#include <asm/cacheops.h>
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#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
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#else
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#define R10KCBARRIER(addr)
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#endif
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#endif /* __ASM_ASM_H */
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