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Merge 666f50fb93 on remote branch

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Change-Id: I67d00d623efdce534bb0a293c7f8ed9a866c58d5
This commit is contained in:
Linux Build Service Account 2021-11-16 22:21:48 -08:00
commit 9300138aad
48 changed files with 15721 additions and 200 deletions
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9
arch/arm/configs/vendor/msm8937-perf_defconfig vendored
View file

@ -370,7 +370,10 @@ CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -379,6 +382,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -515,9 +519,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -670,9 +676,12 @@ CONFIG_LKDTM=m
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CTI=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

16
arch/arm/configs/vendor/msm8937_32go-perf_defconfig vendored
View file

@ -362,7 +362,10 @@ CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -371,6 +374,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -508,9 +512,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -652,3 +658,13 @@ CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_IPC_LOGGING=y
# CONFIG_FTRACE is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

20
arch/arm/configs/vendor/msm8937_32go_defconfig vendored
View file

@ -369,7 +369,10 @@ CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -378,6 +381,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -517,9 +521,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -610,7 +616,6 @@ CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_QCOM_QFPROM=y
CONFIG_STM=y
CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_SENSORS_SSC=y
CONFIG_QCOM_KGSL=y
@ -716,4 +721,15 @@ CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_PANIC_ON_DATA_CORRUPTION=y
CONFIG_DEBUG_USER=y
CONFIG_FORCE_PAGES=y
CONFIG_PID_IN_CONTEXTIDR=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CTI=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

10
arch/arm/configs/vendor/msm8937_defconfig vendored
View file

@ -376,7 +376,10 @@ CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -385,6 +388,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -524,9 +528,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -727,9 +733,13 @@ CONFIG_DEBUG_USER=y
CONFIG_FORCE_PAGES=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CTI=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

388
arch/arm/include/asm/etmv4x.h Normal file
View file

@ -0,0 +1,388 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016, 2018, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ETMV4X_H
#define __ASM_ETMV4X_H
#include <linux/types.h>
/* 32 bit register read for AArch32 */
#define trc_readl(reg) RSYSL_##reg()
#define trc_readq(reg) RSYSL_##reg()
/* 32 bit register write for AArch32 */
#define trc_write(val, reg) WSYS_##reg(val)
#define MRC(op0, op1, crn, crm, op2) \
({ \
uint32_t val; \
asm volatile("mrc p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
val; \
})
#define MCR(val, op0, op1, crn, crm, op2) \
({ \
asm volatile("mcr p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
})
/* Clock and Power Management Register */
#define RSYSL_CPMR_EL1() MRC(15, 7, c15, c0, 5)
#define WSYS_CPMR_EL1(val) MCR(val, 15, 7, c15, c0, 5)
/*
* ETMv4 Registers
*
* Read only
* ETMAUTHSTATUS, ETMDEVARCH, ETMDEVID, ETMIDRn[0-13], ETMOSLSR, ETMSTATR
*
* Write only
* ETMOSLAR
*/
/* 32 bit registers */
#define RSYSL_ETMAUTHSTATUS() MRC(14, 1, c7, c14, 6)
#define RSYSL_ETMAUXCTLR() MRC(14, 1, c0, c6, 0)
#define RSYSL_ETMCCCTLR() MRC(14, 1, c0, c14, 0)
#define RSYSL_ETMCIDCCTLR0() MRC(14, 1, c3, c0, 2)
#define RSYSL_ETMCNTCTLR0() MRC(14, 1, c0, c4, 5)
#define RSYSL_ETMCNTCTLR1() MRC(14, 1, c0, c5, 5)
#define RSYSL_ETMCNTCTLR2() MRC(14, 1, c0, c6, 5)
#define RSYSL_ETMCNTCTLR3() MRC(14, 1, c0, c7, 5)
#define RSYSL_ETMCNTRLDVR0() MRC(14, 1, c0, c0, 5)
#define RSYSL_ETMCNTRLDVR1() MRC(14, 1, c0, c1, 5)
#define RSYSL_ETMCNTRLDVR2() MRC(14, 1, c0, c2, 5)
#define RSYSL_ETMCNTRLDVR3() MRC(14, 1, c0, c3, 5)
#define RSYSL_ETMCNTVR0() MRC(14, 1, c0, c8, 5)
#define RSYSL_ETMCNTVR1() MRC(14, 1, c0, c9, 5)
#define RSYSL_ETMCNTVR2() MRC(14, 1, c0, c10, 5)
#define RSYSL_ETMCNTVR3() MRC(14, 1, c0, c11, 5)
#define RSYSL_ETMCONFIGR() MRC(14, 1, c0, c4, 0)
#define RSYSL_ETMDEVARCH() MRC(14, 1, c7, c15, 6)
#define RSYSL_ETMDEVID() MRC(14, 1, c7, c2, 7)
#define RSYSL_ETMEVENTCTL0R() MRC(14, 1, c0, c8, 0)
#define RSYSL_ETMEVENTCTL1R() MRC(14, 1, c0, c9, 0)
#define RSYSL_ETMEXTINSELR() MRC(14, 1, c0, c8, 4)
#define RSYSL_ETMIDR0() MRC(14, 1, c0, c8, 7)
#define RSYSL_ETMIDR1() MRC(14, 1, c0, c9, 7)
#define RSYSL_ETMIDR10() MRC(14, 1, c0, c2, 6)
#define RSYSL_ETMIDR11() MRC(14, 1, c0, c3, 6)
#define RSYSL_ETMIDR12() MRC(14, 1, c0, c4, 6)
#define RSYSL_ETMIDR13() MRC(14, 1, c0, c5, 6)
#define RSYSL_ETMIDR2() MRC(14, 1, c0, c10, 7)
#define RSYSL_ETMIDR3() MRC(14, 1, c0, c11, 7)
#define RSYSL_ETMIDR4() MRC(14, 1, c0, c12, 7)
#define RSYSL_ETMIDR5() MRC(14, 1, c0, c13, 7)
#define RSYSL_ETMIDR6() MRC(14, 1, c0, c14, 7)
#define RSYSL_ETMIDR7() MRC(14, 1, c0, c15, 7)
#define RSYSL_ETMIDR8() MRC(14, 1, c0, c0, 6)
#define RSYSL_ETMIDR9() MRC(14, 1, c0, c1, 6)
#define RSYSL_ETMIMSPEC0() MRC(14, 1, c0, c0, 7)
#define RSYSL_ETMOSLSR() MRC(14, 1, c1, c1, 4)
#define RSYSL_ETMPRGCTLR() MRC(14, 1, c0, c1, 0)
#define RSYSL_ETMRSCTLR10() MRC(14, 1, c1, c10, 0)
#define RSYSL_ETMRSCTLR11() MRC(14, 1, c1, c11, 0)
#define RSYSL_ETMRSCTLR12() MRC(14, 1, c1, c12, 0)
#define RSYSL_ETMRSCTLR13() MRC(14, 1, c1, c13, 0)
#define RSYSL_ETMRSCTLR14() MRC(14, 1, c1, c14, 0)
#define RSYSL_ETMRSCTLR15() MRC(14, 1, c1, c15, 0)
#define RSYSL_ETMRSCTLR2() MRC(14, 1, c1, c2, 0)
#define RSYSL_ETMRSCTLR3() MRC(14, 1, c1, c3, 0)
#define RSYSL_ETMRSCTLR4() MRC(14, 1, c1, c4, 0)
#define RSYSL_ETMRSCTLR5() MRC(14, 1, c1, c5, 0)
#define RSYSL_ETMRSCTLR6() MRC(14, 1, c1, c6, 0)
#define RSYSL_ETMRSCTLR7() MRC(14, 1, c1, c7, 0)
#define RSYSL_ETMRSCTLR8() MRC(14, 1, c1, c8, 0)
#define RSYSL_ETMRSCTLR9() MRC(14, 1, c1, c9, 0)
#define RSYSL_ETMRSCTLR16() MRC(14, 1, c1, c0, 1)
#define RSYSL_ETMRSCTLR17() MRC(14, 1, c1, c1, 1)
#define RSYSL_ETMRSCTLR18() MRC(14, 1, c1, c2, 1)
#define RSYSL_ETMRSCTLR19() MRC(14, 1, c1, c3, 1)
#define RSYSL_ETMRSCTLR20() MRC(14, 1, c1, c4, 1)
#define RSYSL_ETMRSCTLR21() MRC(14, 1, c1, c5, 1)
#define RSYSL_ETMRSCTLR22() MRC(14, 1, c1, c6, 1)
#define RSYSL_ETMRSCTLR23() MRC(14, 1, c1, c7, 1)
#define RSYSL_ETMRSCTLR24() MRC(14, 1, c1, c8, 1)
#define RSYSL_ETMRSCTLR25() MRC(14, 1, c1, c9, 1)
#define RSYSL_ETMRSCTLR26() MRC(14, 1, c1, c10, 1)
#define RSYSL_ETMRSCTLR27() MRC(14, 1, c1, c11, 1)
#define RSYSL_ETMRSCTLR28() MRC(14, 1, c1, c12, 1)
#define RSYSL_ETMRSCTLR29() MRC(14, 1, c1, c13, 1)
#define RSYSL_ETMRSCTLR30() MRC(14, 1, c1, c14, 1)
#define RSYSL_ETMRSCTLR31() MRC(14, 1, c1, c15, 1)
#define RSYSL_ETMSEQEVR0() MRC(14, 1, c0, c0, 4)
#define RSYSL_ETMSEQEVR1() MRC(14, 1, c0, c1, 4)
#define RSYSL_ETMSEQEVR2() MRC(14, 1, c0, c2, 4)
#define RSYSL_ETMSEQRSTEVR() MRC(14, 1, c0, c6, 4)
#define RSYSL_ETMSEQSTR() MRC(14, 1, c0, c7, 4)
#define RSYSL_ETMSTALLCTLR() MRC(14, 1, c0, c11, 0)
#define RSYSL_ETMSTATR() MRC(14, 1, c0, c3, 0)
#define RSYSL_ETMSYNCPR() MRC(14, 1, c0, c13, 0)
#define RSYSL_ETMTRACEIDR() MRC(14, 1, c0, c0, 1)
#define RSYSL_ETMTSCTLR() MRC(14, 1, c0, c12, 0)
#define RSYSL_ETMVICTLR() MRC(14, 1, c0, c0, 2)
#define RSYSL_ETMVIIECTLR() MRC(14, 1, c0, c1, 2)
#define RSYSL_ETMVISSCTLR() MRC(14, 1, c0, c2, 2)
#define RSYSL_ETMSSCCR0() MRC(14, 1, c1, c0, 2)
#define RSYSL_ETMSSCCR1() MRC(14, 1, c1, c1, 2)
#define RSYSL_ETMSSCCR2() MRC(14, 1, c1, c2, 2)
#define RSYSL_ETMSSCCR3() MRC(14, 1, c1, c3, 2)
#define RSYSL_ETMSSCCR4() MRC(14, 1, c1, c4, 2)
#define RSYSL_ETMSSCCR5() MRC(14, 1, c1, c5, 2)
#define RSYSL_ETMSSCCR6() MRC(14, 1, c1, c6, 2)
#define RSYSL_ETMSSCCR7() MRC(14, 1, c1, c7, 2)
#define RSYSL_ETMSSCSR0() MRC(14, 1, c1, c8, 2)
#define RSYSL_ETMSSCSR1() MRC(14, 1, c1, c9, 2)
#define RSYSL_ETMSSCSR2() MRC(14, 1, c1, c10, 2)
#define RSYSL_ETMSSCSR3() MRC(14, 1, c1, c11, 2)
#define RSYSL_ETMSSCSR4() MRC(14, 1, c1, c12, 2)
#define RSYSL_ETMSSCSR5() MRC(14, 1, c1, c13, 2)
#define RSYSL_ETMSSCSR6() MRC(14, 1, c1, c14, 2)
#define RSYSL_ETMSSCSR7() MRC(14, 1, c1, c15, 2)
#define RSYSL_ETMSSPCICR0() MRC(14, 1, c1, c0, 3)
#define RSYSL_ETMSSPCICR1() MRC(14, 1, c1, c1, 3)
#define RSYSL_ETMSSPCICR2() MRC(14, 1, c1, c2, 3)
#define RSYSL_ETMSSPCICR3() MRC(14, 1, c1, c3, 3)
#define RSYSL_ETMSSPCICR4() MRC(14, 1, c1, c4, 3)
#define RSYSL_ETMSSPCICR5() MRC(14, 1, c1, c5, 3)
#define RSYSL_ETMSSPCICR6() MRC(14, 1, c1, c6, 3)
#define RSYSL_ETMSSPCICR7() MRC(14, 1, c1, c7, 3)
/*
* 64 bit registers, ignore the upper 32bit
* A read from a 32-bit register location using a 64-bit access result
* in the upper 32bits being return as RES0.
*/
#define RSYSL_ETMACATR0() MRC(14, 1, c2, c0, 2)
#define RSYSL_ETMACATR1() MRC(14, 1, c2, c2, 2)
#define RSYSL_ETMACATR2() MRC(14, 1, c2, c4, 2)
#define RSYSL_ETMACATR3() MRC(14, 1, c2, c6, 2)
#define RSYSL_ETMACATR4() MRC(14, 1, c2, c8, 2)
#define RSYSL_ETMACATR5() MRC(14, 1, c2, c10, 2)
#define RSYSL_ETMACATR6() MRC(14, 1, c2, c12, 2)
#define RSYSL_ETMACATR7() MRC(14, 1, c2, c14, 2)
#define RSYSL_ETMACATR8() MRC(14, 1, c2, c0, 3)
#define RSYSL_ETMACATR9() MRC(14, 1, c2, c2, 3)
#define RSYSL_ETMACATR10() MRC(14, 1, c2, c4, 3)
#define RSYSL_ETMACATR11() MRC(14, 1, c2, c6, 3)
#define RSYSL_ETMACATR12() MRC(14, 1, c2, c8, 3)
#define RSYSL_ETMACATR13() MRC(14, 1, c2, c10, 3)
#define RSYSL_ETMACATR14() MRC(14, 1, c2, c12, 3)
#define RSYSL_ETMACATR15() MRC(14, 1, c2, c14, 3)
#define RSYSL_ETMCIDCVR0() MRC(14, 1, c3, c0, 0)
#define RSYSL_ETMCIDCVR1() MRC(14, 1, c3, c2, 0)
#define RSYSL_ETMCIDCVR2() MRC(14, 1, c3, c4, 0)
#define RSYSL_ETMCIDCVR3() MRC(14, 1, c3, c6, 0)
#define RSYSL_ETMCIDCVR4() MRC(14, 1, c3, c8, 0)
#define RSYSL_ETMCIDCVR5() MRC(14, 1, c3, c10, 0)
#define RSYSL_ETMCIDCVR6() MRC(14, 1, c3, c12, 0)
#define RSYSL_ETMCIDCVR7() MRC(14, 1, c3, c14, 0)
#define RSYSL_ETMACVR0() MRC(14, 1, c2, c0, 0)
#define RSYSL_ETMACVR1() MRC(14, 1, c2, c2, 0)
#define RSYSL_ETMACVR2() MRC(14, 1, c2, c4, 0)
#define RSYSL_ETMACVR3() MRC(14, 1, c2, c6, 0)
#define RSYSL_ETMACVR4() MRC(14, 1, c2, c8, 0)
#define RSYSL_ETMACVR5() MRC(14, 1, c2, c10, 0)
#define RSYSL_ETMACVR6() MRC(14, 1, c2, c12, 0)
#define RSYSL_ETMACVR7() MRC(14, 1, c2, c14, 0)
#define RSYSL_ETMACVR8() MRC(14, 1, c2, c0, 1)
#define RSYSL_ETMACVR9() MRC(14, 1, c2, c2, 1)
#define RSYSL_ETMACVR10() MRC(14, 1, c2, c4, 1)
#define RSYSL_ETMACVR11() MRC(14, 1, c2, c6, 1)
#define RSYSL_ETMACVR12() MRC(14, 1, c2, c8, 1)
#define RSYSL_ETMACVR13() MRC(14, 1, c2, c10, 1)
#define RSYSL_ETMACVR14() MRC(14, 1, c2, c12, 1)
#define RSYSL_ETMACVR15() MRC(14, 1, c2, c14, 1)
#define RSYSL_ETMVMIDCVR0() MRC(14, 1, c3, c0, 1)
#define RSYSL_ETMVMIDCVR1() MRC(14, 1, c3, c2, 1)
#define RSYSL_ETMVMIDCVR2() MRC(14, 1, c3, c4, 1)
#define RSYSL_ETMVMIDCVR3() MRC(14, 1, c3, c6, 1)
#define RSYSL_ETMVMIDCVR4() MRC(14, 1, c3, c8, 1)
#define RSYSL_ETMVMIDCVR5() MRC(14, 1, c3, c10, 1)
#define RSYSL_ETMVMIDCVR6() MRC(14, 1, c3, c12, 1)
#define RSYSL_ETMVMIDCVR7() MRC(14, 1, c3, c14, 1)
#define RSYSL_ETMDVCVR0() MRC(14, 1, c2, c0, 4)
#define RSYSL_ETMDVCVR1() MRC(14, 1, c2, c4, 4)
#define RSYSL_ETMDVCVR2() MRC(14, 1, c2, c8, 4)
#define RSYSL_ETMDVCVR3() MRC(14, 1, c2, c12, 4)
#define RSYSL_ETMDVCVR4() MRC(14, 1, c2, c0, 5)
#define RSYSL_ETMDVCVR5() MRC(14, 1, c2, c4, 5)
#define RSYSL_ETMDVCVR6() MRC(14, 1, c2, c8, 5)
#define RSYSL_ETMDVCVR7() MRC(14, 1, c2, c12, 5)
#define RSYSL_ETMDVCMR0() MRC(14, 1, c2, c0, 6)
#define RSYSL_ETMDVCMR1() MRC(14, 1, c2, c4, 6)
#define RSYSL_ETMDVCMR2() MRC(14, 1, c2, c8, 6)
#define RSYSL_ETMDVCMR3() MRC(14, 1, c2, c12, 6)
#define RSYSL_ETMDVCMR4() MRC(14, 1, c2, c0, 7)
#define RSYSL_ETMDVCMR5() MRC(14, 1, c2, c4, 7)
#define RSYSL_ETMDVCMR6() MRC(14, 1, c2, c8, 7)
#define RSYSL_ETMDVCMR7() MRC(14, 1, c2, c12, 7)
/*
* 32 and 64 bit registers
* A write to a 32-bit register location using a 64-bit access result
* in the upper 32bit of access
*/
#define WSYS_ETMAUXCTLR(val) MCR(val, 14, 1, c0, c6, 0)
#define WSYS_ETMACATR0(val) MCR(val, 14, 1, c2, c0, 2)
#define WSYS_ETMACATR1(val) MCR(val, 14, 1, c2, c2, 2)
#define WSYS_ETMACATR2(val) MCR(val, 14, 1, c2, c4, 2)
#define WSYS_ETMACATR3(val) MCR(val, 14, 1, c2, c6, 2)
#define WSYS_ETMACATR4(val) MCR(val, 14, 1, c2, c8, 2)
#define WSYS_ETMACATR5(val) MCR(val, 14, 1, c2, c10, 2)
#define WSYS_ETMACATR6(val) MCR(val, 14, 1, c2, c12, 2)
#define WSYS_ETMACATR7(val) MCR(val, 14, 1, c2, c14, 2)
#define WSYS_ETMACATR8(val) MCR(val, 14, 1, c2, c0, 3)
#define WSYS_ETMACATR9(val) MCR(val, 14, 1, c2, c2, 3)
#define WSYS_ETMACATR10(val) MCR(val, 14, 1, c2, c4, 3)
#define WSYS_ETMACATR11(val) MCR(val, 14, 1, c2, c6, 3)
#define WSYS_ETMACATR12(val) MCR(val, 14, 1, c2, c8, 3)
#define WSYS_ETMACATR13(val) MCR(val, 14, 1, c2, c10, 3)
#define WSYS_ETMACATR14(val) MCR(val, 14, 1, c2, c12, 3)
#define WSYS_ETMACATR15(val) MCR(val, 14, 1, c2, c14, 3)
#define WSYS_ETMACVR0(val) MCR(val, 14, 1, c2, c0, 0)
#define WSYS_ETMACVR1(val) MCR(val, 14, 1, c2, c2, 0)
#define WSYS_ETMACVR2(val) MCR(val, 14, 1, c2, c4, 0)
#define WSYS_ETMACVR3(val) MCR(val, 14, 1, c2, c6, 0)
#define WSYS_ETMACVR4(val) MCR(val, 14, 1, c2, c8, 0)
#define WSYS_ETMACVR5(val) MCR(val, 14, 1, c2, c10, 0)
#define WSYS_ETMACVR6(val) MCR(val, 14, 1, c2, c12, 0)
#define WSYS_ETMACVR7(val) MCR(val, 14, 1, c2, c14, 0)
#define WSYS_ETMACVR8(val) MCR(val, 14, 1, c2, c0, 1)
#define WSYS_ETMACVR9(val) MCR(val, 14, 1, c2, c2, 1)
#define WSYS_ETMACVR10(val) MCR(val, 14, 1, c2, c4, 1)
#define WSYS_ETMACVR11(val) MCR(val, 14, 1, c2, c6, 1)
#define WSYS_ETMACVR12(val) MCR(val, 14, 1, c2, c8, 1)
#define WSYS_ETMACVR13(val) MCR(val, 14, 1, c2, c10, 1)
#define WSYS_ETMACVR14(val) MCR(val, 14, 1, c2, c12, 1)
#define WSYS_ETMACVR15(val) MCR(val, 14, 1, c2, c14, 1)
#define WSYS_ETMCCCTLR(val) MCR(val, 14, 1, c0, c14, 0)
#define WSYS_ETMCIDCCTLR0(val) MCR(val, 14, 1, c3, c0, 2)
#define WSYS_ETMCIDCVR0(val) MCR(val, 14, 1, c3, c0, 0)
#define WSYS_ETMCIDCVR1(val) MCR(val, 14, 1, c3, c2, 0)
#define WSYS_ETMCIDCVR2(val) MCR(val, 14, 1, c3, c4, 0)
#define WSYS_ETMCIDCVR3(val) MCR(val, 14, 1, c3, c6, 0)
#define WSYS_ETMCIDCVR4(val) MCR(val, 14, 1, c3, c8, 0)
#define WSYS_ETMCIDCVR5(val) MCR(val, 14, 1, c3, c10, 0)
#define WSYS_ETMCIDCVR6(val) MCR(val, 14, 1, c3, c12, 0)
#define WSYS_ETMCIDCVR7(val) MCR(val, 14, 1, c3, c14, 0)
#define WSYS_ETMCNTCTLR0(val) MCR(val, 14, 1, c0, c4, 5)
#define WSYS_ETMCNTCTLR1(val) MCR(val, 14, 1, c0, c5, 5)
#define WSYS_ETMCNTCTLR2(val) MCR(val, 14, 1, c0, c6, 5)
#define WSYS_ETMCNTCTLR3(val) MCR(val, 14, 1, c0, c7, 5)
#define WSYS_ETMCNTRLDVR0(val) MCR(val, 14, 1, c0, c0, 5)
#define WSYS_ETMCNTRLDVR1(val) MCR(val, 14, 1, c0, c1, 5)
#define WSYS_ETMCNTRLDVR2(val) MCR(val, 14, 1, c0, c2, 5)
#define WSYS_ETMCNTRLDVR3(val) MCR(val, 14, 1, c0, c3, 5)
#define WSYS_ETMCNTVR0(val) MCR(val, 14, 1, c0, c8, 5)
#define WSYS_ETMCNTVR1(val) MCR(val, 14, 1, c0, c9, 5)
#define WSYS_ETMCNTVR2(val) MCR(val, 14, 1, c0, c10, 5)
#define WSYS_ETMCNTVR3(val) MCR(val, 14, 1, c0, c11, 5)
#define WSYS_ETMCONFIGR(val) MCR(val, 14, 1, c0, c4, 0)
#define WSYS_ETMEVENTCTL0R(val) MCR(val, 14, 1, c0, c8, 0)
#define WSYS_ETMEVENTCTL1R(val) MCR(val, 14, 1, c0, c9, 0)
#define WSYS_ETMEXTINSELR(val) MCR(val, 14, 1, c0, c8, 4)
#define WSYS_ETMIMSPEC0(val) MCR(val, 14, 1, c0, c0, 7)
#define WSYS_ETMOSLAR(val) MCR(val, 14, 1, c1, c0, 4)
#define WSYS_ETMPRGCTLR(val) MCR(val, 14, 1, c0, c1, 0)
#define WSYS_ETMRSCTLR10(val) MCR(val, 14, 1, c1, c10, 0)
#define WSYS_ETMRSCTLR11(val) MCR(val, 14, 1, c1, c11, 0)
#define WSYS_ETMRSCTLR12(val) MCR(val, 14, 1, c1, c12, 0)
#define WSYS_ETMRSCTLR13(val) MCR(val, 14, 1, c1, c13, 0)
#define WSYS_ETMRSCTLR14(val) MCR(val, 14, 1, c1, c14, 0)
#define WSYS_ETMRSCTLR15(val) MCR(val, 14, 1, c1, c15, 0)
#define WSYS_ETMRSCTLR2(val) MCR(val, 14, 1, c1, c2, 0)
#define WSYS_ETMRSCTLR3(val) MCR(val, 14, 1, c1, c3, 0)
#define WSYS_ETMRSCTLR4(val) MCR(val, 14, 1, c1, c4, 0)
#define WSYS_ETMRSCTLR5(val) MCR(val, 14, 1, c1, c5, 0)
#define WSYS_ETMRSCTLR6(val) MCR(val, 14, 1, c1, c6, 0)
#define WSYS_ETMRSCTLR7(val) MCR(val, 14, 1, c1, c7, 0)
#define WSYS_ETMRSCTLR8(val) MCR(val, 14, 1, c1, c8, 0)
#define WSYS_ETMRSCTLR9(val) MCR(val, 14, 1, c1, c9, 0)
#define WSYS_ETMRSCTLR16(val) MCR(val, 14, 1, c1, c0, 1)
#define WSYS_ETMRSCTLR17(val) MCR(val, 14, 1, c1, c1, 1)
#define WSYS_ETMRSCTLR18(val) MCR(val, 14, 1, c1, c2, 1)
#define WSYS_ETMRSCTLR19(val) MCR(val, 14, 1, c1, c3, 1)
#define WSYS_ETMRSCTLR20(val) MCR(val, 14, 1, c1, c4, 1)
#define WSYS_ETMRSCTLR21(val) MCR(val, 14, 1, c1, c5, 1)
#define WSYS_ETMRSCTLR22(val) MCR(val, 14, 1, c1, c6, 1)
#define WSYS_ETMRSCTLR23(val) MCR(val, 14, 1, c1, c7, 1)
#define WSYS_ETMRSCTLR24(val) MCR(val, 14, 1, c1, c8, 1)
#define WSYS_ETMRSCTLR25(val) MCR(val, 14, 1, c1, c9, 1)
#define WSYS_ETMRSCTLR26(val) MCR(val, 14, 1, c1, c10, 1)
#define WSYS_ETMRSCTLR27(val) MCR(val, 14, 1, c1, c11, 1)
#define WSYS_ETMRSCTLR28(val) MCR(val, 14, 1, c1, c12, 1)
#define WSYS_ETMRSCTLR29(val) MCR(val, 14, 1, c1, c13, 1)
#define WSYS_ETMRSCTLR30(val) MCR(val, 14, 1, c1, c14, 1)
#define WSYS_ETMRSCTLR31(val) MCR(val, 14, 1, c1, c15, 1)
#define WSYS_ETMSEQEVR0(val) MCR(val, 14, 1, c0, c0, 4)
#define WSYS_ETMSEQEVR1(val) MCR(val, 14, 1, c0, c1, 4)
#define WSYS_ETMSEQEVR2(val) MCR(val, 14, 1, c0, c2, 4)
#define WSYS_ETMSEQRSTEVR(val) MCR(val, 14, 1, c0, c6, 4)
#define WSYS_ETMSEQSTR(val) MCR(val, 14, 1, c0, c7, 4)
#define WSYS_ETMSTALLCTLR(val) MCR(val, 14, 1, c0, c11, 0)
#define WSYS_ETMSYNCPR(val) MCR(val, 14, 1, c0, c13, 0)
#define WSYS_ETMTRACEIDR(val) MCR(val, 14, 1, c0, c0, 1)
#define WSYS_ETMTSCTLR(val) MCR(val, 14, 1, c0, c12, 0)
#define WSYS_ETMVICTLR(val) MCR(val, 14, 1, c0, c0, 2)
#define WSYS_ETMVIIECTLR(val) MCR(val, 14, 1, c0, c1, 2)
#define WSYS_ETMVISSCTLR(val) MCR(val, 14, 1, c0, c2, 2)
#define WSYS_ETMVMIDCVR0(val) MCR(val, 14, 1, c3, c0, 1)
#define WSYS_ETMVMIDCVR1(val) MCR(val, 14, 1, c3, c2, 1)
#define WSYS_ETMVMIDCVR2(val) MCR(val, 14, 1, c3, c4, 1)
#define WSYS_ETMVMIDCVR3(val) MCR(val, 14, 1, c3, c6, 1)
#define WSYS_ETMVMIDCVR4(val) MCR(val, 14, 1, c3, c8, 1)
#define WSYS_ETMVMIDCVR5(val) MCR(val, 14, 1, c3, c10, 1)
#define WSYS_ETMVMIDCVR6(val) MCR(val, 14, 1, c3, c12, 1)
#define WSYS_ETMVMIDCVR7(val) MCR(val, 14, 1, c3, c14, 1)
#define WSYS_ETMDVCVR0(val) MCR(val, 14, 1, c2, c0, 4)
#define WSYS_ETMDVCVR1(val) MCR(val, 14, 1, c2, c4, 4)
#define WSYS_ETMDVCVR2(val) MCR(val, 14, 1, c2, c8, 4)
#define WSYS_ETMDVCVR3(val) MCR(val, 14, 1, c2, c12, 4)
#define WSYS_ETMDVCVR4(val) MCR(val, 14, 1, c2, c0, 5)
#define WSYS_ETMDVCVR5(val) MCR(val, 14, 1, c2, c4, 5)
#define WSYS_ETMDVCVR6(val) MCR(val, 14, 1, c2, c8, 5)
#define WSYS_ETMDVCVR7(val) MCR(val, 14, 1, c2, c12, 5)
#define WSYS_ETMDVCMR0(val) MCR(val, 14, 1, c2, c0, 6)
#define WSYS_ETMDVCMR1(val) MCR(val, 14, 1, c2, c4, 6)
#define WSYS_ETMDVCMR2(val) MCR(val, 14, 1, c2, c8, 6)
#define WSYS_ETMDVCMR3(val) MCR(val, 14, 1, c2, c12, 6)
#define WSYS_ETMDVCMR4(val) MCR(val, 14, 1, c2, c0, 7)
#define WSYS_ETMDVCMR5(val) MCR(val, 14, 1, c2, c4, 7)
#define WSYS_ETMDVCMR6(val) MCR(val, 14, 1, c2, c8, 7)
#define WSYS_ETMDVCMR7(val) MCR(val, 14, 1, c2, c12, 7)
#define WSYS_ETMSSCCR0(val) MCR(val, 14, 1, c1, c0, 2)
#define WSYS_ETMSSCCR1(val) MCR(val, 14, 1, c1, c1, 2)
#define WSYS_ETMSSCCR2(val) MCR(val, 14, 1, c1, c2, 2)
#define WSYS_ETMSSCCR3(val) MCR(val, 14, 1, c1, c3, 2)
#define WSYS_ETMSSCCR4(val) MCR(val, 14, 1, c1, c4, 2)
#define WSYS_ETMSSCCR5(val) MCR(val, 14, 1, c1, c5, 2)
#define WSYS_ETMSSCCR6(val) MCR(val, 14, 1, c1, c6, 2)
#define WSYS_ETMSSCCR7(val) MCR(val, 14, 1, c1, c7, 2)
#define WSYS_ETMSSCSR0(val) MCR(val, 14, 1, c1, c8, 2)
#define WSYS_ETMSSCSR1(val) MCR(val, 14, 1, c1, c9, 2)
#define WSYS_ETMSSCSR2(val) MCR(val, 14, 1, c1, c10, 2)
#define WSYS_ETMSSCSR3(val) MCR(val, 14, 1, c1, c11, 2)
#define WSYS_ETMSSCSR4(val) MCR(val, 14, 1, c1, c12, 2)
#define WSYS_ETMSSCSR5(val) MCR(val, 14, 1, c1, c13, 2)
#define WSYS_ETMSSCSR6(val) MCR(val, 14, 1, c1, c14, 2)
#define WSYS_ETMSSCSR7(val) MCR(val, 14, 1, c1, c15, 2)
#define WSYS_ETMSSPCICR0(val) MCR(val, 14, 1, c1, c0, 3)
#define WSYS_ETMSSPCICR1(val) MCR(val, 14, 1, c1, c1, 3)
#define WSYS_ETMSSPCICR2(val) MCR(val, 14, 1, c1, c2, 3)
#define WSYS_ETMSSPCICR3(val) MCR(val, 14, 1, c1, c3, 3)
#define WSYS_ETMSSPCICR4(val) MCR(val, 14, 1, c1, c4, 3)
#define WSYS_ETMSSPCICR5(val) MCR(val, 14, 1, c1, c5, 3)
#define WSYS_ETMSSPCICR6(val) MCR(val, 14, 1, c1, c6, 3)
#define WSYS_ETMSSPCICR7(val) MCR(val, 14, 1, c1, c7, 3)
#endif

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arch/arm/include/asm/hardware/debugv8.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016, 2018, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_HARDWARE_DEBUGV8_H
#define __ASM_HARDWARE_DEBUGV8_H
#include <linux/types.h>
/* Accessors for CP14 registers */
#define dbg_read(reg) RCP14_##reg()
#define dbg_write(val, reg) WCP14_##reg(val)
/* MRC14 registers */
#define MRC14(op1, crn, crm, op2) \
({ \
uint32_t val; \
asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
val; \
})
/* MCR14 registers */
#define MCR14(val, op1, crn, crm, op2) \
({ \
asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
})
/*
* Debug Registers
*
* Read only
* DBGDIDR, DBGDSCRint, DBGDTRRXint, DBGDRAR, DBGOSLSR, DBGOSSRR, DBGDSAR,
* DBGAUTHSTATUS, DBGDEVID2, DBGDEVID1, DBGDEVID
*
* Write only
* DBGDTRTXint, DBGOSLAR
*/
#define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
#define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
#define RCP14_DBGDCCINT() MRC14(0, c0, c2, 0)
#define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
#define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
#define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
#define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
#define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
#define RCP14_DBGDTRTXext() MRC14(0, c0, c3, 2)
#define RCP14_DBGOSECCR() MRC14(0, c0, c6, 2)
#define RCP14_DBGBVR0() MRC14(0, c0, c0, 4)
#define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
#define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
#define RCP14_DBGBVR3() MRC14(0, c0, c3, 4)
#define RCP14_DBGBVR4() MRC14(0, c0, c4, 4)
#define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
#define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
#define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
#define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
#define RCP14_DBGBVR9() MRC14(0, c0, c9, 4)
#define RCP14_DBGBVR10() MRC14(0, c0, c10, 4)
#define RCP14_DBGBVR11() MRC14(0, c0, c11, 4)
#define RCP14_DBGBVR12() MRC14(0, c0, c12, 4)
#define RCP14_DBGBVR13() MRC14(0, c0, c13, 4)
#define RCP14_DBGBVR14() MRC14(0, c0, c14, 4)
#define RCP14_DBGBVR15() MRC14(0, c0, c15, 4)
#define RCP14_DBGBCR0() MRC14(0, c0, c0, 5)
#define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
#define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
#define RCP14_DBGBCR3() MRC14(0, c0, c3, 5)
#define RCP14_DBGBCR4() MRC14(0, c0, c4, 5)
#define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
#define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
#define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
#define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
#define RCP14_DBGBCR9() MRC14(0, c0, c9, 5)
#define RCP14_DBGBCR10() MRC14(0, c0, c10, 5)
#define RCP14_DBGBCR11() MRC14(0, c0, c11, 5)
#define RCP14_DBGBCR12() MRC14(0, c0, c12, 5)
#define RCP14_DBGBCR13() MRC14(0, c0, c13, 5)
#define RCP14_DBGBCR14() MRC14(0, c0, c14, 5)
#define RCP14_DBGBCR15() MRC14(0, c0, c15, 5)
#define RCP14_DBGWVR0() MRC14(0, c0, c0, 6)
#define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
#define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
#define RCP14_DBGWVR3() MRC14(0, c0, c3, 6)
#define RCP14_DBGWVR4() MRC14(0, c0, c4, 6)
#define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
#define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
#define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
#define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
#define RCP14_DBGWVR9() MRC14(0, c0, c9, 6)
#define RCP14_DBGWVR10() MRC14(0, c0, c10, 6)
#define RCP14_DBGWVR11() MRC14(0, c0, c11, 6)
#define RCP14_DBGWVR12() MRC14(0, c0, c12, 6)
#define RCP14_DBGWVR13() MRC14(0, c0, c13, 6)
#define RCP14_DBGWVR14() MRC14(0, c0, c14, 6)
#define RCP14_DBGWVR15() MRC14(0, c0, c15, 6)
#define RCP14_DBGWCR0() MRC14(0, c0, c0, 7)
#define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
#define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
#define RCP14_DBGWCR3() MRC14(0, c0, c3, 7)
#define RCP14_DBGWCR4() MRC14(0, c0, c4, 7)
#define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
#define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
#define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
#define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
#define RCP14_DBGWCR9() MRC14(0, c0, c9, 7)
#define RCP14_DBGWCR10() MRC14(0, c0, c10, 7)
#define RCP14_DBGWCR11() MRC14(0, c0, c11, 7)
#define RCP14_DBGWCR12() MRC14(0, c0, c12, 7)
#define RCP14_DBGWCR13() MRC14(0, c0, c13, 7)
#define RCP14_DBGWCR14() MRC14(0, c0, c14, 7)
#define RCP14_DBGWCR15() MRC14(0, c0, c15, 7)
#define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
#define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
#define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
#define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
#define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
#define RCP14_DBGBXVR4() MRC14(0, c1, c4, 1)
#define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
#define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
#define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
#define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
#define RCP14_DBGBXVR9() MRC14(0, c1, c9, 1)
#define RCP14_DBGBXVR10() MRC14(0, c1, c10, 1)
#define RCP14_DBGBXVR11() MRC14(0, c1, c11, 1)
#define RCP14_DBGBXVR12() MRC14(0, c1, c12, 1)
#define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1)
#define RCP14_DBGBXVR14() MRC14(0, c1, c14, 1)
#define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1)
#define RCP14_DBGOSLSR() MRC14(0, c1, c1, 4)
#define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
#define RCP14_DBGOSDLR() MRC14(0, c1, c3, 4)
#define RCP14_DBGPRCR() MRC14(0, c1, c4, 4)
#define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
#define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
#define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
#define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
#define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
#define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
#define RCP14_DBGDEVID2() MRC14(0, c7, c0, 7)
#define RCP14_DBGDEVID1() MRC14(0, c7, c1, 7)
#define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
#define WCP14_DBGDCCINT(val) MCR14(val, 0, c0, c2, 0)
#define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
#define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
#define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0)
#define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2)
#define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
#define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2)
#define WCP14_DBGOSECCR(val) MCR14(val, 0, c0, c6, 2)
#define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4)
#define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4)
#define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4)
#define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4)
#define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4)
#define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
#define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
#define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4)
#define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
#define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4)
#define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4)
#define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4)
#define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4)
#define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4)
#define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4)
#define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4)
#define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5)
#define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5)
#define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5)
#define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5)
#define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5)
#define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
#define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
#define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5)
#define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
#define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5)
#define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5)
#define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5)
#define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5)
#define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5)
#define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5)
#define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5)
#define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6)
#define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6)
#define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6)
#define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6)
#define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6)
#define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6)
#define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6)
#define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6)
#define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
#define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6)
#define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6)
#define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6)
#define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6)
#define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6)
#define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6)
#define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6)
#define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7)
#define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7)
#define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7)
#define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7)
#define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7)
#define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7)
#define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7)
#define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7)
#define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
#define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7)
#define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7)
#define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7)
#define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7)
#define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7)
#define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7)
#define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7)
#define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1)
#define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1)
#define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1)
#define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1)
#define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1)
#define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1)
#define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1)
#define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1)
#define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1)
#define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1)
#define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1)
#define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1)
#define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1)
#define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1)
#define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1)
#define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1)
#define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4)
#define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4)
#define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4)
#define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4)
#define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4)
#define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6)
#define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6)
#endif

1
arch/arm/include/asm/hw_breakpoint.h
View file

@ -53,6 +53,7 @@ static inline void decode_ctrl_reg(u32 reg,
#define ARM_DEBUG_ARCH_V7_MM 4
#define ARM_DEBUG_ARCH_V7_1 5
#define ARM_DEBUG_ARCH_V8 6
#define ARM_DEBUG_ARCH_V8_8 8
/* Breakpoint */
#define ARM_BREAKPOINT_EXECUTE 0

1
arch/arm64/configs/vendor/kona_defconfig vendored
View file

@ -370,6 +370,7 @@ CONFIG_TABLET_USB_HANWANG=y
CONFIG_TABLET_USB_KBTAB=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_FTS=y
CONFIG_TOUCHSCREEN_NT36XXX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_QPNP_POWER_ON=y
CONFIG_INPUT_QTI_HAPTICS=y

10
arch/arm64/configs/vendor/msm8937-perf_defconfig vendored
View file

@ -365,7 +365,10 @@ CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -374,6 +377,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -508,9 +512,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -651,7 +657,11 @@ CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

11
arch/arm64/configs/vendor/msm8937_defconfig vendored
View file

@ -374,7 +374,10 @@ CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_VM_BMS=y
CONFIG_QPNP_LINEAR_CHARGER=y
CONFIG_SMB1351_USB_CHARGER=y
CONFIG_SMB1360_CHARGER_FG=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y
@ -383,6 +386,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_LOW_LIMITS=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_QCOM_SPMI_TEMP_ALARM=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_THERMAL_TSENS=y
CONFIG_QTI_ADC_TM=y
@ -521,9 +525,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
CONFIG_LEDS_QTI_TRI_LED=y
CONFIG_LEDS_QPNP_FLASH_V2=y
CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
CONFIG_LEDS_QPNP_VIBRATOR=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_DMADEVICES=y
CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
@ -716,12 +722,15 @@ CONFIG_ATOMIC64_SELFTEST=m
CONFIG_MEMTEST=y
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_PANIC_ON_DATA_CORRUPTION=y
CONFIG_PID_IN_CONTEXTIDR=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CTI=y
CONFIG_CORESIGHT_TPDA=y
CONFIG_CORESIGHT_TPDM=y
CONFIG_CORESIGHT_HWEVENT=y
CONFIG_CORESIGHT_DUMMY=y
CONFIG_CORESIGHT_REMOTE_ETM=y
CONFIG_CORESIGHT_TGU=y

49
drivers/dma-buf/dma-buf.c
View file

@ -102,35 +102,12 @@ static char *dmabuffs_dname(struct dentry *dentry, char *buffer, int buflen)
dentry->d_name.name, ret > 0 ? name : "");
}
static const struct dentry_operations dma_buf_dentry_ops = {
.d_dname = dmabuffs_dname,
};
static struct vfsmount *dma_buf_mnt;
static struct dentry *dma_buf_fs_mount(struct file_system_type *fs_type,
int flags, const char *name, void *data)
{
return mount_pseudo(fs_type, "dmabuf:", NULL, &dma_buf_dentry_ops,
DMA_BUF_MAGIC);
}
static struct file_system_type dma_buf_fs_type = {
.name = "dmabuf",
.mount = dma_buf_fs_mount,
.kill_sb = kill_anon_super,
};
static int dma_buf_release(struct inode *inode, struct file *file)
static void dma_buf_release(struct dentry *dentry)
{
struct dma_buf *dmabuf;
struct dentry *dentry = file->f_path.dentry;
int dtor_ret = 0;
if (!is_dma_buf_file(file))
return -EINVAL;
dmabuf = file->private_data;
dmabuf = dentry->d_fsdata;
spin_lock(&dentry->d_lock);
dentry->d_fsdata = NULL;
@ -167,9 +144,28 @@ static int dma_buf_release(struct inode *inode, struct file *file)
module_put(dmabuf->owner);
dmabuf_dent_put(dmabuf);
return 0;
}
static const struct dentry_operations dma_buf_dentry_ops = {
.d_dname = dmabuffs_dname,
.d_release = dma_buf_release,
};
static struct vfsmount *dma_buf_mnt;
static struct dentry *dma_buf_fs_mount(struct file_system_type *fs_type,
int flags, const char *name, void *data)
{
return mount_pseudo(fs_type, "dmabuf:", NULL, &dma_buf_dentry_ops,
DMA_BUF_MAGIC);
}
static struct file_system_type dma_buf_fs_type = {
.name = "dmabuf",
.mount = dma_buf_fs_mount,
.kill_sb = kill_anon_super,
};
static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
{
struct dma_buf *dmabuf;
@ -488,7 +484,6 @@ static void dma_buf_show_fdinfo(struct seq_file *m, struct file *file)
}
static const struct file_operations dma_buf_fops = {
.release = dma_buf_release,
.mmap = dma_buf_mmap_internal,
.llseek = dma_buf_llseek,
.poll = dma_buf_poll,

35
drivers/gpu/msm/adreno_a6xx.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/firmware.h>
@ -89,9 +89,27 @@ static u32 a6xx_ifpc_pwrup_reglist[] = {
};
/* Applicable to a620 and a650 */
static u32 a650_ifpc_pwrup_reglist[] = {
A6XX_CP_PROTECT_REG+32,
A6XX_CP_PROTECT_REG+33,
A6XX_CP_PROTECT_REG+34,
A6XX_CP_PROTECT_REG+35,
A6XX_CP_PROTECT_REG+36,
A6XX_CP_PROTECT_REG+37,
A6XX_CP_PROTECT_REG+38,
A6XX_CP_PROTECT_REG+39,
A6XX_CP_PROTECT_REG+40,
A6XX_CP_PROTECT_REG+41,
A6XX_CP_PROTECT_REG+42,
A6XX_CP_PROTECT_REG+43,
A6XX_CP_PROTECT_REG+44,
A6XX_CP_PROTECT_REG+45,
A6XX_CP_PROTECT_REG+46,
A6XX_CP_PROTECT_REG+47,
};
static u32 a650_pwrup_reglist[] = {
A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
A6XX_CP_PROTECT_REG + 47, /* Programmed for infinite span */
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
@ -351,14 +369,21 @@ struct a6xx_reglist_list {
static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
{
struct a6xx_reglist_list reglist[3];
struct a6xx_reglist_list reglist[4];
void *ptr = adreno_dev->pwrup_reglist.hostptr;
struct cpu_gpu_lock *lock = ptr;
int items = 0, i, j;
u32 *dest = ptr + sizeof(*lock);
u16 list_offset = 0;
/* Static IFPC-only registers */
reglist[items++] = REGLIST(a6xx_ifpc_pwrup_reglist);
reglist[items] = REGLIST(a6xx_ifpc_pwrup_reglist);
list_offset += reglist[items++].count * 2;
if (adreno_is_a650_family(adreno_dev)) {
reglist[items] = REGLIST(a650_ifpc_pwrup_reglist);
list_offset += reglist[items++].count * 2;
}
/* Static IFPC + preemption registers */
reglist[items++] = REGLIST(a6xx_pwrup_reglist);
@ -401,7 +426,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
* all the lists and list_offset should be specified as the size in
* dwords of the first entry in the list.
*/
lock->list_offset = reglist[0].count * 2;
lock->list_offset = list_offset;
}
/*

81
drivers/hwtracing/coresight/coresight-tmc.c
View file

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2012,2017-2019, The Linux Foundation. All rights reserved.
/* Copyright (c) 2012,2017-2019,2021, The Linux Foundation. All rights reserved.
*
* Description: CoreSight Trace Memory Controller driver
*/
@ -23,10 +23,13 @@
#include <linux/of.h>
#include <linux/coresight.h>
#include <linux/amba/bus.h>
#include <soc/qcom/memory_dump.h>
#include "coresight-priv.h"
#include "coresight-tmc.h"
#define TMC_REG_DUMP_MAGIC 0x42445953
void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
{
/* Ensure formatter, unformatter and hardware fifo are empty */
@ -56,10 +59,84 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
tmc_wait_for_tmcready(drvdata);
}
static void __tmc_reg_dump(struct tmc_drvdata *drvdata)
{
struct dump_vaddr_entry *dump_entry;
struct msm_dump_data *dump_data;
uint32_t *reg_buf;
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
dump_entry = get_msm_dump_ptr(MSM_DUMP_DATA_TMC_ETR_REG);
dev_dbg(drvdata->dev, "%s: TMC ETR dump entry ptr is %pK\n",
__func__, dump_entry);
} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETB ||
drvdata->config_type == TMC_CONFIG_TYPE_ETF) {
dump_entry = get_msm_dump_ptr(MSM_DUMP_DATA_TMC_ETF_REG);
dev_dbg(drvdata->dev, "%s: TMC ETF dump entry ptr is %pK\n",
__func__, dump_entry);
} else
return;
if (dump_entry == NULL)
return;
reg_buf = (uint32_t *)(dump_entry->dump_vaddr);
dump_data = dump_entry->dump_data_vaddr;
if (reg_buf == NULL || dump_data == NULL)
return;
dev_dbg(drvdata->dev, "%s: TMC dump reg ptr is %pK, dump_data is %pK\n",
__func__, reg_buf, dump_data);
reg_buf[1] = readl_relaxed(drvdata->base + TMC_RSZ);
reg_buf[3] = readl_relaxed(drvdata->base + TMC_STS);
reg_buf[5] = readl_relaxed(drvdata->base + TMC_RRP);
reg_buf[6] = readl_relaxed(drvdata->base + TMC_RWP);
reg_buf[7] = readl_relaxed(drvdata->base + TMC_TRG);
reg_buf[8] = readl_relaxed(drvdata->base + TMC_CTL);
reg_buf[10] = readl_relaxed(drvdata->base + TMC_MODE);
reg_buf[11] = readl_relaxed(drvdata->base + TMC_LBUFLEVEL);
reg_buf[12] = readl_relaxed(drvdata->base + TMC_CBUFLEVEL);
reg_buf[13] = readl_relaxed(drvdata->base + TMC_BUFWM);
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
reg_buf[14] = readl_relaxed(drvdata->base + TMC_RRPHI);
reg_buf[15] = readl_relaxed(drvdata->base + TMC_RWPHI);
reg_buf[68] = readl_relaxed(drvdata->base + TMC_AXICTL);
reg_buf[70] = readl_relaxed(drvdata->base + TMC_DBALO);
reg_buf[71] = readl_relaxed(drvdata->base + TMC_DBAHI);
}
reg_buf[192] = readl_relaxed(drvdata->base + TMC_FFSR);
reg_buf[193] = readl_relaxed(drvdata->base + TMC_FFCR);
reg_buf[194] = readl_relaxed(drvdata->base + TMC_PSCR);
reg_buf[1000] = readl_relaxed(drvdata->base + CORESIGHT_CLAIMSET);
reg_buf[1001] = readl_relaxed(drvdata->base + CORESIGHT_CLAIMCLR);
reg_buf[1005] = readl_relaxed(drvdata->base + CORESIGHT_LSR);
reg_buf[1006] = readl_relaxed(drvdata->base + CORESIGHT_AUTHSTATUS);
reg_buf[1010] = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
reg_buf[1011] = readl_relaxed(drvdata->base + CORESIGHT_DEVTYPE);
reg_buf[1012] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR4);
reg_buf[1013] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR5);
reg_buf[1014] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR6);
reg_buf[1015] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR7);
reg_buf[1016] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
reg_buf[1017] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR1);
reg_buf[1018] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR2);
reg_buf[1019] = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR3);
reg_buf[1020] = readl_relaxed(drvdata->base + CORESIGHT_COMPIDR0);
reg_buf[1021] = readl_relaxed(drvdata->base + CORESIGHT_COMPIDR1);
reg_buf[1022] = readl_relaxed(drvdata->base + CORESIGHT_COMPIDR2);
reg_buf[1023] = readl_relaxed(drvdata->base + CORESIGHT_COMPIDR3);
dump_data->magic = TMC_REG_DUMP_MAGIC;
}
void tmc_enable_hw(struct tmc_drvdata *drvdata)
{
drvdata->enable = true;
writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
if (drvdata->force_reg_dump)
__tmc_reg_dump(drvdata);
}
void tmc_disable_hw(struct tmc_drvdata *drvdata)
@ -650,6 +727,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
return -EPROBE_DEFER;
}
}
if (of_property_read_bool(drvdata->dev->of_node, "qcom,force-reg-dump"))
drvdata->force_reg_dump = true;
desc.pdata = pdata;
desc.dev = dev;

1
drivers/hwtracing/coresight/coresight-tmc.h
View file

@ -268,6 +268,7 @@ struct tmc_drvdata {
struct idr idr;
struct mutex idr_mutex;
struct etr_buf *perf_buf;
bool force_reg_dump;
};
struct etr_buf_operations {

159
drivers/media/platform/msm/npu/npu_mgr.c
View file

@ -15,6 +15,7 @@
#include "npu_common.h"
#include <soc/qcom/subsystem_notif.h>
#include <soc/qcom/subsystem_restart.h>
#include <linux/reboot.h>
/* -------------------------------------------------------------------------
* Defines
@ -279,6 +280,50 @@ int load_fw(struct npu_device *npu_dev)
return 0;
}
static void complete_pending_commands(struct npu_host_ctx *host_ctx)
{
struct npu_network *network = NULL;
struct npu_kevent kevt;
struct npu_network_cmd *cmd;
struct npu_misc_cmd *misc_cmd;
int i;
/* flush all pending npu cmds */
for (i = 0; i < MAX_LOADED_NETWORK; i++) {
network = &host_ctx->networks[i];
if (!network->is_valid || !network->fw_error)
continue;
if (network->is_async) {
NPU_DBG("async cmd, queue ssr event\n");
kevt.evt.type = MSM_NPU_EVENT_TYPE_SSR;
kevt.evt.u.ssr.network_hdl =
network->network_hdl;
if (npu_queue_event(network->client, &kevt))
NPU_ERR("queue npu event failed\n");
while (!list_empty(&network->cmd_list)) {
cmd = list_first_entry(&network->cmd_list,
struct npu_network_cmd, list);
npu_dequeue_network_cmd(network, cmd);
npu_free_network_cmd(host_ctx, cmd);
}
} else {
list_for_each_entry(cmd, &network->cmd_list, list) {
NPU_INFO("complete network %llx trans_id %d\n",
network->id, cmd->trans_id);
complete(&cmd->cmd_done);
}
}
}
list_for_each_entry(misc_cmd, &host_ctx->misc_cmd_list, list) {
NPU_INFO("complete misc cmd trans_id %d\n",
misc_cmd->trans_id);
complete(&misc_cmd->cmd_done);
}
}
int unload_fw(struct npu_device *npu_dev)
{
struct npu_host_ctx *host_ctx = &npu_dev->host_ctx;
@ -294,7 +339,9 @@ int unload_fw(struct npu_device *npu_dev)
mutex_unlock(&host_ctx->lock);
return 0;
} else if (host_ctx->fw_state == FW_ENABLED) {
NPU_ERR("fw is enabled now, can't be unloaded\n");
NPU_ERR("fw is enabled now, device is shutting down?\n");
host_ctx->dev_shuttingdown = true;
complete_pending_commands(host_ctx);
mutex_unlock(&host_ctx->lock);
return -EBUSY;
}
@ -315,6 +362,11 @@ static int enable_fw_nolock(struct npu_device *npu_dev)
int ret = 0;
uint32_t reg_val;
if (host_ctx->dev_shuttingdown) {
NPU_ERR("device is shutting down, ignore enable request\n");
return -EIO;
}
if (host_ctx->fw_state == FW_UNLOADED) {
ret = load_fw_nolock(npu_dev,
host_ctx->auto_pil_disable ? true : false);
@ -470,6 +522,11 @@ static int disable_fw_nolock(struct npu_device *npu_dev)
if (host_ctx->fw_ref_cnt > 0)
return ret;
if (host_ctx->dev_shuttingdown) {
NPU_ERR("device is shutting down, ignore disable request\n");
return -EIO;
}
/* turn on auto ACK for warm shuts down */
npu_cc_reg_write(npu_dev, NPU_CC_NPU_CPC_RSC_CTRL, 3);
reinit_completion(&host_ctx->fw_shutdown_done);
@ -712,6 +769,24 @@ static int npu_panic_handler(struct notifier_block *this,
return NOTIFY_DONE;
}
static int npu_reboot_handler(struct notifier_block *this,
unsigned long code, void *unused)
{
struct npu_host_ctx *host_ctx =
container_of(this, struct npu_host_ctx, reboot_nb);
NPU_INFO("Device is rebooting with code %d\n", code);
if ((code == NOTIFY_DONE) || (code == SYS_POWER_OFF)) {
mutex_lock(&host_ctx->lock);
host_ctx->dev_shuttingdown = true;
complete_pending_commands(host_ctx);
mutex_unlock(&host_ctx->lock);
}
return NOTIFY_DONE;
}
static void npu_update_pwr_work(struct work_struct *work)
{
int ret;
@ -764,6 +839,13 @@ int npu_host_init(struct npu_device *npu_dev)
goto fail;
}
host_ctx->reboot_nb.notifier_call = npu_reboot_handler;
ret = register_reboot_notifier(&host_ctx->reboot_nb);
if (ret) {
NPU_ERR("register reboot notifier failed\n");
goto fail;
}
host_ctx->panic_nb.notifier_call = npu_panic_handler;
ret = atomic_notifier_chain_register(&panic_notifier_list,
&host_ctx->panic_nb);
@ -839,6 +921,7 @@ int npu_host_init(struct npu_device *npu_dev)
if (host_ctx->notif_hdle)
subsys_notif_unregister_notifier(host_ctx->notif_hdle,
&host_ctx->nb);
unregister_reboot_notifier(&host_ctx->reboot_nb);
mutex_destroy(&host_ctx->lock);
return ret;
}
@ -854,6 +937,7 @@ void npu_host_deinit(struct npu_device *npu_dev)
destroy_workqueue(host_ctx->wq);
destroy_workqueue(host_ctx->wq_pri);
subsys_notif_unregister_notifier(host_ctx->notif_hdle, &host_ctx->nb);
unregister_reboot_notifier(&host_ctx->reboot_nb);
mutex_destroy(&host_ctx->lock);
}
@ -947,9 +1031,6 @@ static int host_error_hdlr(struct npu_device *npu_dev, bool force)
{
struct npu_host_ctx *host_ctx = &npu_dev->host_ctx;
struct npu_network *network = NULL;
struct npu_kevent kevt;
struct npu_network_cmd *cmd;
struct npu_misc_cmd *misc_cmd;
bool fw_alive = true;
int i, ret = 0;
@ -961,6 +1042,12 @@ static int host_error_hdlr(struct npu_device *npu_dev, bool force)
return 0;
}
if (host_ctx->dev_shuttingdown) {
NPU_INFO("device is shutting down, igonre error handler\n");
mutex_unlock(&host_ctx->lock);
return -EIO;
}
if (host_ctx->wdg_irq_sts) {
NPU_INFO("watchdog irq triggered\n");
fw_alive = false;
@ -1070,41 +1157,8 @@ static int host_error_hdlr(struct npu_device *npu_dev, bool force)
}
complete(&host_ctx->fw_deinit_done);
complete_pending_commands(host_ctx);
/* flush all pending npu cmds */
for (i = 0; i < MAX_LOADED_NETWORK; i++) {
network = &host_ctx->networks[i];
if (!network->is_valid || !network->fw_error)
continue;
if (network->is_async) {
NPU_DBG("async cmd, queue ssr event\n");
kevt.evt.type = MSM_NPU_EVENT_TYPE_SSR;
kevt.evt.u.ssr.network_hdl =
network->network_hdl;
if (npu_queue_event(network->client, &kevt))
NPU_ERR("queue npu event failed\n");
while (!list_empty(&network->cmd_list)) {
cmd = list_first_entry(&network->cmd_list,
struct npu_network_cmd, list);
npu_dequeue_network_cmd(network, cmd);
npu_free_network_cmd(host_ctx, cmd);
}
} else {
list_for_each_entry(cmd, &network->cmd_list, list) {
NPU_DBG("complete network %llx trans_id %d\n",
network->id, cmd->trans_id);
complete(&cmd->cmd_done);
}
}
}
list_for_each_entry(misc_cmd, &host_ctx->misc_cmd_list, list) {
NPU_DBG("complete misc cmd trans_id %d\n",
misc_cmd->trans_id);
complete(&misc_cmd->cmd_done);
}
mutex_unlock(&host_ctx->lock);
return ret;
@ -2086,6 +2140,7 @@ static int npu_send_network_cmd(struct npu_device *npu_dev,
WARN_ON(!mutex_is_locked(&host_ctx->lock));
if (network->fw_error || host_ctx->fw_error ||
host_ctx->dev_shuttingdown ||
(host_ctx->fw_state != FW_ENABLED)) {
NPU_ERR("fw is in error state or disabled\n");
ret = -EIO;
@ -2111,7 +2166,8 @@ static int npu_send_misc_cmd(struct npu_device *npu_dev, uint32_t q_idx,
WARN_ON(!mutex_is_locked(&host_ctx->lock));
if (host_ctx->fw_error || (host_ctx->fw_state != FW_ENABLED)) {
if (host_ctx->fw_error || host_ctx->dev_shuttingdown ||
(host_ctx->fw_state != FW_ENABLED)) {
NPU_ERR("fw is in error state or disabled\n");
ret = -EIO;
} else {
@ -2548,6 +2604,12 @@ int32_t npu_host_load_network_v2(struct npu_client *client,
goto free_load_cmd;
}
if (host_ctx->dev_shuttingdown) {
ret = -EIO;
NPU_ERR("device is shutting down\n");
goto free_load_cmd;
}
if (!ret) {
NPU_ERR("npu: NPU_IPC_CMD_LOAD time out %lld:%d\n",
network->id, load_cmd->trans_id);
@ -2633,6 +2695,11 @@ int32_t npu_host_unload_network(struct npu_client *client,
goto free_network;
}
if (host_ctx->dev_shuttingdown) {
NPU_ERR("device is shutting down, skip unload network in fw\n");
goto free_network;
}
NPU_DBG("Unload network %lld\n", network->id);
/* prepare IPC packet for UNLOAD */
unload_packet.header.cmd_type = NPU_IPC_CMD_UNLOAD;
@ -2686,7 +2753,7 @@ int32_t npu_host_unload_network(struct npu_client *client,
mutex_lock(&host_ctx->lock);
if (network->fw_error) {
if (network->fw_error || host_ctx->dev_shuttingdown) {
ret = -EIO;
NPU_ERR("fw is in error state during unload network\n");
goto free_network;
@ -2779,6 +2846,12 @@ int32_t npu_host_exec_network_v2(struct npu_client *client,
goto exec_v2_done;
}
if (host_ctx->dev_shuttingdown) {
NPU_ERR("device is shutting down\n");
ret = -EIO;
goto exec_v2_done;
}
if (network->is_async && !async_ioctl) {
NPU_ERR("network is in async mode\n");
ret = -EINVAL;
@ -2869,6 +2942,12 @@ int32_t npu_host_exec_network_v2(struct npu_client *client,
goto free_exec_cmd;
}
if (host_ctx->dev_shuttingdown) {
ret = -EIO;
NPU_ERR("device is shutting down during execute_v2 network\n");
goto free_exec_cmd;
}
if (!ret) {
NPU_ERR("npu: %llx:%d NPU_IPC_CMD_EXECUTE_V2 time out\n",
network->id, exec_cmd->trans_id);

4
drivers/media/platform/msm/npu/npu_mgr.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _NPU_MGR_H
@ -131,10 +131,12 @@ struct npu_host_ctx {
uint32_t err_irq_sts;
uint32_t wdg_irq_sts;
bool fw_error;
bool dev_shuttingdown;
bool cancel_work;
bool app_crashed;
struct notifier_block nb;
struct notifier_block panic_nb;
struct notifier_block reboot_nb;
void *notif_hdle;
spinlock_t bridge_mbox_lock;
bool bridge_mbox_pwr_on;

2
drivers/media/usb/uvc/uvc_video.c
View file

@ -26,6 +26,8 @@
#include "uvcvideo.h"
#define CONFIG_DMA_NONCOHERENT 1
/* ------------------------------------------------------------------------
* UVC Controls
*/

63
drivers/net/wireless/cnss2/pci.c
View file

@ -130,6 +130,13 @@ static struct cnss_pci_reg qdss_csr[] = {
{ NULL },
};
static struct cnss_pci_reg pci_scratch[] = {
{ "PCIE_SCRATCH_0", PCIE_SCRATCH_0_SOC_PCIE_REG },
{ "PCIE_SCRATCH_1", PCIE_SCRATCH_1_SOC_PCIE_REG },
{ "PCIE_SCRATCH_2", PCIE_SCRATCH_2_SOC_PCIE_REG },
{ NULL },
};
static struct cnss_misc_reg wcss_reg_access_seq[] = {
{0, QCA6390_GCC_DEBUG_CLK_CTL, 0},
{1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802},
@ -722,6 +729,35 @@ static int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up)
return ret;
}
static void cnss_pci_soc_scratch_reg_dump(struct cnss_pci_data *pci_priv)
{
u32 reg_offset, val;
int i;
switch (pci_priv->device_id) {
case QCA6490_DEVICE_ID:
break;
default:
return;
}
if (in_interrupt() || irqs_disabled())
return;
if (cnss_pci_check_link_status(pci_priv))
return;
cnss_pr_dbg("Start to dump SOC Scratch registers\n");
for (i = 0; pci_scratch[i].name; i++) {
reg_offset = pci_scratch[i].offset;
if (cnss_pci_reg_read(pci_priv, reg_offset, &val))
return;
cnss_pr_dbg("PCIE_SOC_REG_%s = 0x%x\n",
pci_scratch[i].name, val);
}
}
int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv)
{
int ret = 0;
@ -841,6 +877,7 @@ int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv)
jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT));
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
return 0;
}
@ -1758,6 +1795,7 @@ static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv)
return;
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_misc_reg_dump(pci_priv, pci_priv->wcss_reg,
pci_priv->wcss_reg_size, "wcss");
cnss_pci_misc_reg_dump(pci_priv, pci_priv->pcie_reg,
@ -1775,6 +1813,7 @@ static void cnss_pci_dump_mhi_reg(struct cnss_pci_data *pci_priv)
return;
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
}
static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv)
@ -1885,9 +1924,9 @@ static void cnss_pci_dump_qca6390_sram_mem(struct cnss_pci_data *pci_priv)
sbl_log_size = (sbl_log_size > QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
if (sbl_log_start < QCA6390_V2_SBL_DATA_START ||
sbl_log_start > QCA6390_V2_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6390_V2_SBL_DATA_END)
if (sbl_log_start < SRAM_START ||
sbl_log_start > SRAM_END ||
(sbl_log_start + sbl_log_size) > SRAM_END)
goto out;
cnss_pr_dbg("Dumping SBL log data\n");
@ -1955,17 +1994,11 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
if (plat_priv->device_version.major_version == FW_V2_NUMBER) {
if (sbl_log_start < QCA6490_V2_SBL_DATA_START ||
sbl_log_start > QCA6490_V2_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6490_V2_SBL_DATA_END)
goto out;
} else {
if (sbl_log_start < QCA6490_V1_SBL_DATA_START ||
sbl_log_start > QCA6490_V1_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6490_V1_SBL_DATA_END)
goto out;
}
if (sbl_log_start < SRAM_START ||
sbl_log_start > SRAM_END ||
(sbl_log_start + sbl_log_size) > SRAM_END)
goto out;
cnss_pr_dbg("Dumping SBL log data");
for (i = 0; i < sbl_log_size; i += sizeof(val)) {
@ -4178,6 +4211,7 @@ static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)
return;
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10);
@ -4621,6 +4655,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t)
cnss_pr_err("Unable to collect ramdumps due to abrupt reset\n");
mhi_debug_reg_dump(mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT);
}

18
drivers/net/wireless/cnss2/reg.h
View file

@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
#ifndef _CNSS_REG_H
#define _CNSS_REG_H
@ -267,12 +267,8 @@
#define QCA6390_SYSPM_DBG_BUS_SEL_REG 0x1F82008
#define QCA6390_SYSPM_WCSSAON_SR_STATUS 0x1F8200C
#define QCA6490_DEBUG_PBL_LOG_SRAM_START 0x1403D58
#define QCA6490_DEBUG_PBL_LOG_SRAM_START 0x01403DA0
#define QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40
#define QCA6490_V1_SBL_DATA_START 0x143b000
#define QCA6490_V1_SBL_DATA_END (0x143b000 + 0x00011000)
#define QCA6490_V2_SBL_DATA_START 0x1435000
#define QCA6490_V2_SBL_DATA_END (0x1435000 + 0x00011000)
#define QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48
#define QCA6490_TCSR_PBL_LOGGING_REG 0x01B000F8
#define QCA6490_PCIE_BHI_ERRDBG2_REG 0x01E0E238
@ -282,12 +278,18 @@
#define QCA6390_DEBUG_PBL_LOG_SRAM_START 0x01403D58
#define QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE 80
#define QCA6390_V2_SBL_DATA_START 0x016c8580
#define QCA6390_V2_SBL_DATA_END (0x016c8580 + 0x00011000)
#define QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE 44
#define QCA6390_TCSR_PBL_LOGGING_REG 0x01B000F8
#define QCA6390_PCIE_BHI_ERRDBG2_REG 0x01E0E238
#define QCA6390_PCIE_BHI_ERRDBG3_REG 0x01E0E23C
#define QCA6390_PBL_WLAN_BOOT_CFG 0x01E22B34
#define QCA6390_PBL_BOOTSTRAP_STATUS 0x01910008
#define SRAM_START 0x01400000
#define SRAM_END 0x01800000
/* PCIE SOC scratch registers, address same for QCA6390 & QCA6490*/
#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040
#define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
#define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
#endif

16
drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2019,2021 The Linux Foundation. All rights reserved.
*/
#include "ipa_i.h"
@ -90,6 +90,15 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,
0 : 1;
}
}
/* Check the pointer and header length to avoid
* dangerous overflow in HW
*/
if (unlikely(!entry->hdr || !entry->hdr->offset_entry ||
!entry->offset_entry ||
entry->hdr->hdr_len == 0 ||
entry->hdr->hdr_len >
ipa_hdr_bin_sz[IPA_HDR_BIN_MAX - 1]))
return -EINVAL;
ret = ipahal_cp_proc_ctx_to_hw_buff(entry->type, mem->base,
entry->offset_entry->offset,
@ -747,7 +756,7 @@ int __ipa3_del_hdr(u32 hdr_hdl, bool by_user)
return 0;
}
if (entry->is_hdr_proc_ctx) {
if (entry->is_hdr_proc_ctx || entry->proc_ctx) {
dma_unmap_single(ipa3_ctx->pdev,
entry->phys_base,
entry->hdr_len,
@ -1076,6 +1085,7 @@ int ipa3_reset_hdr(bool user_only)
if (ipa3_id_find(entry->id) == NULL) {
mutex_unlock(&ipa3_ctx->lock);
IPAERR_RL("Invalid header ID\n");
WARN_ON_RATELIMIT_IPA(1);
return -EFAULT;
}
@ -1086,6 +1096,7 @@ int ipa3_reset_hdr(bool user_only)
entry->phys_base,
entry->hdr_len,
DMA_TO_DEVICE);
entry->proc_ctx->hdr = NULL;
entry->proc_ctx = NULL;
} else {
/* move the offset entry to free list */
@ -1143,6 +1154,7 @@ int ipa3_reset_hdr(bool user_only)
if (ipa3_id_find(ctx_entry->id) == NULL) {
mutex_unlock(&ipa3_ctx->lock);
IPAERR_RL("Invalid proc header ID\n");
WARN_ON_RATELIMIT_IPA(1);
return -EFAULT;
}

11
drivers/platform/msm/ipa/ipa_v3/ipa_odl.c
View file

@ -250,6 +250,7 @@ int ipa3_send_adpl_msg(unsigned long skb_data)
list_add_tail(&msg->link, &ipa3_odl_ctx->adpl_msg_list);
atomic_inc(&ipa3_odl_ctx->stats.numer_in_queue);
mutex_unlock(&ipa3_odl_ctx->adpl_msg_lock);
wake_up(&ipa3_odl_ctx->adpl_msg_waitq);
IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_rx_pkt);
return 0;
@ -534,7 +535,9 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
int ret = 0;
char __user *start = buf;
struct ipa3_push_msg_odl *msg;
DEFINE_WAIT_FUNC(wait, woken_wake_function);
add_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait);
while (1) {
IPADBG_LOW("Writing message to adpl pipe\n");
if (!ipa3_odl_ctx->odl_state.odl_open)
@ -579,9 +582,6 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_tx_diag_pkt);
kfree(msg);
msg = NULL;
} else {
ret = -EAGAIN;
break;
}
ret = -EAGAIN;
@ -594,9 +594,9 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
if (start != buf)
break;
wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT);
}
remove_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait);
if (start != buf && ret != -EFAULT)
ret = buf - start;
@ -672,6 +672,7 @@ int ipa_odl_init(void)
odl_cdev = ipa3_odl_ctx->odl_cdev;
INIT_LIST_HEAD(&ipa3_odl_ctx->adpl_msg_list);
init_waitqueue_head(&ipa3_odl_ctx->adpl_msg_waitq);
mutex_init(&ipa3_odl_ctx->adpl_msg_lock);
mutex_init(&ipa3_odl_ctx->pipe_lock);

1
drivers/platform/msm/ipa/ipa_v3/ipa_odl.h
View file

@ -58,6 +58,7 @@ struct ipa_odl_context {
bool odl_ctl_msg_wq_flag;
struct ipa3_odlstats stats;
u32 odl_pm_hdl;
wait_queue_head_t adpl_msg_waitq;
};
struct ipa3_push_msg_odl {

5
drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
View file

@ -484,8 +484,11 @@ static int ipa3_qmi_send_req_wait(struct qmi_handle *client_handle,
req_desc->ei_array,
req);
if (unlikely(!ipa_q6_clnt))
if (unlikely(!ipa_q6_clnt)) {
mutex_unlock(&ipa3_qmi_lock);
return -EINVAL;
}
mutex_unlock(&ipa3_qmi_lock);
if (ret < 0) {

30
drivers/power/supply/qcom/Kconfig
View file

@ -40,6 +40,25 @@ config QPNP_SMBLITE
as fuel gauge and USB.
VBUS regulator is registered for supporting OTG.
config QPNP_VM_BMS
tristate "QPNP Voltage-Mode Battery Monitoring System driver"
depends on MFD_SPMI_PMIC
help
Say Y here to enable support for QPNP chip vm-bms device.
The voltage-mode (vm) BMS driver uses periodic VBATT
readings from the battery to calculate the State of
Charge.
config QPNP_LINEAR_CHARGER
tristate "QPNP Linear Charger driver"
depends on MFD_SPMI_PMIC
help
Say Y here to enable the Linear battery charger which supports USB
detection and charging. The driver also offers relevant information
to userspace via the power supply framework.
The power supply framework is used to communicate battery and
usb properties to userspace and other driver consumers like USB.
config SMB138X_CHARGER
tristate "SMB138X Battery Charger"
depends on MFD_I2C_PMIC
@ -73,6 +92,17 @@ config SMB1351_USB_CHARGER
notification support. The driver controls SMB1351 via I2C and
supports device-tree interface.
config SMB1360_CHARGER_FG
tristate "SMB1360 Charger and Fuel Gauge"
depends on I2C
help
Say Y to include support for SMB1360 Charger and Fuel Gauge.
SMB1360 is a single path switching mode charger capable of charging
the battery with 1.5Amps of current. It supports a fuel gauge which
uses voltage and coloumb counting for state of charge reporting.
The driver reports the status via the power supply framework.
A status change triggers an IRQ via the device STAT pin.
config SMB1355_SLAVE_CHARGER
tristate "SMB1355 Slave Battery Charger"
depends on MFD_I2C_PMIC

4
drivers/power/supply/qcom/Makefile
View file

@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SMB1360_CHARGER_FG) += smb1360-charger-fg.o
obj-$(CONFIG_QPNP_SMB5) += step-chg-jeita.o battery.o qpnp-smb5.o smb5-lib.o pmic-voter.o storm-watch.o schgm-flash.o
obj-$(CONFIG_SMB1390_CHARGE_PUMP_PSY) += smb1390-charger-psy.o pmic-voter.o
obj-$(CONFIG_SMB1355_SLAVE_CHARGER) += smb1355-charger.o pmic-voter.o
@ -13,3 +13,5 @@ obj-$(CONFIG_QPNP_QG) += qpnp-qg.o pmic-voter.o qg-util.o qg-soc.o qg-sdam.o q
obj-$(CONFIG_HL6111R) += hl6111r.o
obj-$(CONFIG_SMB1398_CHARGER) += smb1398-charger.o pmic-voter.o
obj-$(CONFIG_QPNP_SMBLITE) += step-chg-jeita.o battery.o qpnp-smblite.o smblite-lib.o pmic-voter.o storm-watch.o schgm-flashlite.o
obj-$(CONFIG_QPNP_VM_BMS) += qpnp-vm-bms.o batterydata-lib.o batterydata-interface.o
obj-$(CONFIG_QPNP_LINEAR_CHARGER) += qpnp-linear-charger.o

211
drivers/power/supply/qcom/batterydata-interface.c Normal file
View file

@ -0,0 +1,211 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, 2018, 2021, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "BATTERY: %s: " fmt, __func__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/sched.h>
#include <linux/cdev.h>
#include <linux/fs.h>
#include <linux/fcntl.h>
#include <linux/uaccess.h>
#include <linux/batterydata-lib.h>
#include <linux/batterydata-interface.h>
struct battery_data {
dev_t dev_no;
struct class *battery_class;
struct device *battery_device;
struct cdev battery_cdev;
struct bms_battery_data *profile;
};
static struct battery_data *the_battery;
static int battery_data_open(struct inode *inode, struct file *file)
{
struct battery_data *battery = container_of(inode->i_cdev,
struct battery_data, battery_cdev);
pr_debug("battery_data device opened\n");
file->private_data = battery;
return 0;
}
static long battery_data_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct battery_data *battery = file->private_data;
struct battery_params __user *bp_user =
(struct battery_params __user *)arg;
struct battery_params bp;
int soc, rbatt_sf, slope, fcc_mah;
int rc = 0;
if (!battery->profile) {
pr_err("Battery data not set!\n");
return -EINVAL;
}
if (copy_from_user(&bp, bp_user, sizeof(bp))) {
pr_err("copy_from_user failed\n");
return -EFAULT;
}
switch (cmd) {
case BPIOCXSOC:
soc = interpolate_pc(battery->profile->pc_temp_ocv_lut,
bp.batt_temp, bp.ocv_uv / 1000);
rc = put_user(soc, &bp_user->soc);
if (rc) {
pr_err("BPIOCXSOC: Failed to 'put_user' rc=%d\n", rc);
goto ret_err;
}
pr_debug("BPIOCXSOC: ocv=%d batt_temp=%d soc=%d\n",
bp.ocv_uv / 1000, bp.batt_temp, soc);
break;
case BPIOCXRBATT:
rbatt_sf = interpolate_scalingfactor(
battery->profile->rbatt_sf_lut,
bp.batt_temp, bp.soc);
rc = put_user(rbatt_sf, &bp_user->rbatt_sf);
if (rc) {
pr_err("BPIOCXRBATT: Failed to 'put_user' rc=%d\n", rc);
goto ret_err;
}
pr_debug("BPIOCXRBATT: soc=%d batt_temp=%d rbatt_sf=%d\n",
bp.soc, bp.batt_temp, rbatt_sf);
break;
case BPIOCXSLOPE:
slope = interpolate_slope(battery->profile->pc_temp_ocv_lut,
bp.batt_temp, bp.soc);
rc = put_user(slope, &bp_user->slope);
if (rc) {
pr_err("BPIOCXSLOPE: Failed to 'put_user' rc=%d\n", rc);
goto ret_err;
}
pr_debug("BPIOCXSLOPE: soc=%d batt_temp=%d slope=%d\n",
bp.soc, bp.batt_temp, slope);
break;
case BPIOCXFCC:
fcc_mah = interpolate_fcc(battery->profile->fcc_temp_lut,
bp.batt_temp);
rc = put_user(fcc_mah, &bp_user->fcc_mah);
if (rc) {
pr_err("BPIOCXFCC: Failed to 'put_user' rc=%d\n", rc);
goto ret_err;
}
pr_debug("BPIOCXFCC: batt_temp=%d fcc_mah=%d\n",
bp.batt_temp, fcc_mah);
break;
default:
pr_err("IOCTL %d not supported\n", cmd);
rc = -EINVAL;
}
ret_err:
return rc;
}
static int battery_data_release(struct inode *inode, struct file *file)
{
pr_debug("battery_data device closed\n");
return 0;
}
static const struct file_operations battery_data_fops = {
.owner = THIS_MODULE,
.open = battery_data_open,
.unlocked_ioctl = battery_data_ioctl,
.compat_ioctl = battery_data_ioctl,
.release = battery_data_release,
};
int config_battery_data(struct bms_battery_data *profile)
{
if (!the_battery) {
pr_err("Battery data not initialized\n");
return -ENODEV;
}
the_battery->profile = profile;
pr_debug("Battery profile set - %s\n",
the_battery->profile->battery_type);
return 0;
}
static int batterydata_init(void)
{
int rc;
struct battery_data *battery;
battery = kzalloc(sizeof(*battery), GFP_KERNEL);
if (!battery)
return -ENOMEM;
/* character device to access the battery-data from userspace */
rc = alloc_chrdev_region(&battery->dev_no, 0, 1, "battery_data");
if (rc) {
pr_err("Unable to allocate chrdev rc=%d\n", rc);
return rc;
}
cdev_init(&battery->battery_cdev, &battery_data_fops);
rc = cdev_add(&battery->battery_cdev, battery->dev_no, 1);
if (rc) {
pr_err("Unable to add battery_cdev rc=%d\n", rc);
goto unregister_chrdev;
}
battery->battery_class = class_create(THIS_MODULE, "battery_data");
if (IS_ERR_OR_NULL(battery->battery_class)) {
pr_err("Fail to create battery class\n");
rc = -ENODEV;
goto delete_cdev;
}
battery->battery_device = device_create(battery->battery_class,
NULL, battery->dev_no,
NULL, "battery_data");
if (IS_ERR(battery->battery_device)) {
pr_err("Fail to create battery_device device\n");
rc = -ENODEV;
goto delete_cdev;
}
the_battery = battery;
pr_info("Battery-data device created!\n");
return 0;
delete_cdev:
cdev_del(&battery->battery_cdev);
unregister_chrdev:
unregister_chrdev_region(battery->dev_no, 1);
the_battery = NULL;
return rc;
}
subsys_initcall(batterydata_init);
static void batterydata_exit(void)
{
if (the_battery) {
device_destroy(the_battery->battery_class, the_battery->dev_no);
cdev_del(&the_battery->battery_cdev);
unregister_chrdev_region(the_battery->dev_no, 1);
}
kfree(the_battery);
the_battery = NULL;
}
module_exit(batterydata_exit);
MODULE_DESCRIPTION("Battery-data Interface driver");
MODULE_LICENSE("GPL v2");

485
drivers/power/supply/qcom/batterydata-lib.c Normal file
View file

@ -0,0 +1,485 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2014, 2018, 2021, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/module.h>
#include <linux/batterydata-lib.h>
int linear_interpolate(int y0, int x0, int y1, int x1, int x)
{
if (y0 == y1 || x == x0)
return y0;
if (x1 == x0 || x == x1)
return y1;
return y0 + ((y1 - y0) * (x - x0) / (x1 - x0));
}
static int interpolate_single_lut_scaled(struct single_row_lut *lut,
int x, int scale)
{
int i, result;
if (x < lut->x[0] * scale) {
pr_debug("x %d less than known range return y = %d lut = %pS\n",
x, lut->y[0], lut);
return lut->y[0];
}
if (x > lut->x[lut->cols - 1] * scale) {
pr_debug("x %d more than known range return y = %d lut = %pS\n",
x, lut->y[lut->cols - 1], lut);
return lut->y[lut->cols - 1];
}
for (i = 0; i < lut->cols; i++)
if (x <= lut->x[i] * scale)
break;
if (x == lut->x[i] * scale) {
result = lut->y[i];
} else {
result = linear_interpolate(
lut->y[i - 1],
lut->x[i - 1] * scale,
lut->y[i],
lut->x[i] * scale,
x);
}
return result;
}
int interpolate_fcc(struct single_row_lut *fcc_temp_lut, int batt_temp)
{
return interpolate_single_lut_scaled(fcc_temp_lut,
batt_temp,
DEGC_SCALE);
}
int interpolate_scalingfactor_fcc(struct single_row_lut *fcc_sf_lut,
int cycles)
{
/*
* sf table could be null when no battery aging data is available, in
* that case return 100%
*/
if (fcc_sf_lut)
return interpolate_single_lut_scaled(fcc_sf_lut, cycles, 1);
else
return 100;
}
int interpolate_scalingfactor(struct sf_lut *sf_lut, int row_entry, int pc)
{
int i, scalefactorrow1, scalefactorrow2, scalefactor, rows, cols;
int row1 = 0;
int row2 = 0;
/*
* sf table could be null when no battery aging data is available, in
* that case return 100%
*/
if (!sf_lut)
return 100;
rows = sf_lut->rows;
cols = sf_lut->cols;
if (pc > sf_lut->percent[0]) {
pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
row1 = 0;
row2 = 0;
} else if (pc < sf_lut->percent[rows - 1]) {
pr_debug("pc %d less than known pc ranges for sf\n", pc);
row1 = rows - 1;
row2 = rows - 1;
} else {
for (i = 0; i < rows; i++) {
if (pc == sf_lut->percent[i]) {
row1 = i;
row2 = i;
break;
}
if (pc > sf_lut->percent[i]) {
row1 = i - 1;
row2 = i;
break;
}
}
}
if (row_entry < sf_lut->row_entries[0] * DEGC_SCALE)
row_entry = sf_lut->row_entries[0] * DEGC_SCALE;
if (row_entry > sf_lut->row_entries[cols - 1] * DEGC_SCALE)
row_entry = sf_lut->row_entries[cols - 1] * DEGC_SCALE;
for (i = 0; i < cols; i++)
if (row_entry <= sf_lut->row_entries[i] * DEGC_SCALE)
break;
if (row_entry == sf_lut->row_entries[i] * DEGC_SCALE) {
scalefactor = linear_interpolate(
sf_lut->sf[row1][i],
sf_lut->percent[row1],
sf_lut->sf[row2][i],
sf_lut->percent[row2],
pc);
return scalefactor;
}
scalefactorrow1 = linear_interpolate(
sf_lut->sf[row1][i - 1],
sf_lut->row_entries[i - 1] * DEGC_SCALE,
sf_lut->sf[row1][i],
sf_lut->row_entries[i] * DEGC_SCALE,
row_entry);
scalefactorrow2 = linear_interpolate(
sf_lut->sf[row2][i - 1],
sf_lut->row_entries[i - 1] * DEGC_SCALE,
sf_lut->sf[row2][i],
sf_lut->row_entries[i] * DEGC_SCALE,
row_entry);
scalefactor = linear_interpolate(
scalefactorrow1,
sf_lut->percent[row1],
scalefactorrow2,
sf_lut->percent[row2],
pc);
return scalefactor;
}
/* get ocv given a soc -- reverse lookup */
int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp, int pc)
{
int i, ocvrow1, ocvrow2, ocv, rows, cols;
int row1 = 0;
int row2 = 0;
rows = pc_temp_ocv->rows;
cols = pc_temp_ocv->cols;
if (pc > pc_temp_ocv->percent[0]) {
pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
row1 = 0;
row2 = 0;
} else if (pc < pc_temp_ocv->percent[rows - 1]) {
pr_debug("pc %d less than known pc ranges for sf\n", pc);
row1 = rows - 1;
row2 = rows - 1;
} else {
for (i = 0; i < rows; i++) {
if (pc == pc_temp_ocv->percent[i]) {
row1 = i;
row2 = i;
break;
}
if (pc > pc_temp_ocv->percent[i]) {
row1 = i - 1;
row2 = i;
break;
}
}
}
if (batt_temp < pc_temp_ocv->temp[0] * DEGC_SCALE)
batt_temp = pc_temp_ocv->temp[0] * DEGC_SCALE;
if (batt_temp > pc_temp_ocv->temp[cols - 1] * DEGC_SCALE)
batt_temp = pc_temp_ocv->temp[cols - 1] * DEGC_SCALE;
for (i = 0; i < cols; i++)
if (batt_temp <= pc_temp_ocv->temp[i] * DEGC_SCALE)
break;
if (batt_temp == pc_temp_ocv->temp[i] * DEGC_SCALE) {
ocv = linear_interpolate(
pc_temp_ocv->ocv[row1][i],
pc_temp_ocv->percent[row1],
pc_temp_ocv->ocv[row2][i],
pc_temp_ocv->percent[row2],
pc);
return ocv;
}
ocvrow1 = linear_interpolate(
pc_temp_ocv->ocv[row1][i - 1],
pc_temp_ocv->temp[i - 1] * DEGC_SCALE,
pc_temp_ocv->ocv[row1][i],
pc_temp_ocv->temp[i] * DEGC_SCALE,
batt_temp);
ocvrow2 = linear_interpolate(
pc_temp_ocv->ocv[row2][i - 1],
pc_temp_ocv->temp[i - 1] * DEGC_SCALE,
pc_temp_ocv->ocv[row2][i],
pc_temp_ocv->temp[i] * DEGC_SCALE,
batt_temp);
ocv = linear_interpolate(
ocvrow1,
pc_temp_ocv->percent[row1],
ocvrow2,
pc_temp_ocv->percent[row2],
pc);
return ocv;
}
int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp, int ocv)
{
int i, j, pcj, pcj_minus_one, pc;
int rows = pc_temp_ocv->rows;
int cols = pc_temp_ocv->cols;
if (batt_temp < pc_temp_ocv->temp[0] * DEGC_SCALE) {
pr_debug("batt_temp %d < known temp range\n", batt_temp);
batt_temp = pc_temp_ocv->temp[0] * DEGC_SCALE;
}
if (batt_temp > pc_temp_ocv->temp[cols - 1] * DEGC_SCALE) {
pr_debug("batt_temp %d > known temp range\n", batt_temp);
batt_temp = pc_temp_ocv->temp[cols - 1] * DEGC_SCALE;
}
for (j = 0; j < cols; j++)
if (batt_temp <= pc_temp_ocv->temp[j] * DEGC_SCALE)
break;
if (batt_temp == pc_temp_ocv->temp[j] * DEGC_SCALE) {
/* found an exact match for temp in the table */
if (ocv >= pc_temp_ocv->ocv[0][j])
return pc_temp_ocv->percent[0];
if (ocv <= pc_temp_ocv->ocv[rows - 1][j])
return pc_temp_ocv->percent[rows - 1];
for (i = 0; i < rows; i++) {
if (ocv >= pc_temp_ocv->ocv[i][j]) {
if (ocv == pc_temp_ocv->ocv[i][j])
return pc_temp_ocv->percent[i];
pc = linear_interpolate(
pc_temp_ocv->percent[i],
pc_temp_ocv->ocv[i][j],
pc_temp_ocv->percent[i - 1],
pc_temp_ocv->ocv[i - 1][j],
ocv);
return pc;
}
}
}
/*
* batt_temp is within temperature for
* column j-1 and j
*/
if (ocv >= pc_temp_ocv->ocv[0][j])
return pc_temp_ocv->percent[0];
if (ocv <= pc_temp_ocv->ocv[rows - 1][j - 1])
return pc_temp_ocv->percent[rows - 1];
pcj_minus_one = 0;
pcj = 0;
for (i = 0; i < rows-1; i++) {
if (pcj == 0
&& is_between(pc_temp_ocv->ocv[i][j],
pc_temp_ocv->ocv[i+1][j], ocv)) {
pcj = linear_interpolate(
pc_temp_ocv->percent[i],
pc_temp_ocv->ocv[i][j],
pc_temp_ocv->percent[i + 1],
pc_temp_ocv->ocv[i+1][j],
ocv);
}
if (pcj_minus_one == 0
&& is_between(pc_temp_ocv->ocv[i][j-1],
pc_temp_ocv->ocv[i+1][j-1], ocv)) {
pcj_minus_one = linear_interpolate(
pc_temp_ocv->percent[i],
pc_temp_ocv->ocv[i][j-1],
pc_temp_ocv->percent[i + 1],
pc_temp_ocv->ocv[i+1][j-1],
ocv);
}
if (pcj && pcj_minus_one) {
pc = linear_interpolate(
pcj_minus_one,
pc_temp_ocv->temp[j-1] * DEGC_SCALE,
pcj,
pc_temp_ocv->temp[j] * DEGC_SCALE,
batt_temp);
return pc;
}
}
if (pcj)
return pcj;
if (pcj_minus_one)
return pcj_minus_one;
pr_debug("%d ocv wasn't found for temp %d in the LUT returning 100%%\n",
ocv, batt_temp);
return 100;
}
int interpolate_slope(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp, int pc)
{
int i, ocvrow1, ocvrow2, rows, cols;
int row1 = 0;
int row2 = 0;
int slope;
rows = pc_temp_ocv->rows;
cols = pc_temp_ocv->cols;
if (pc >= pc_temp_ocv->percent[0]) {
pr_debug("pc %d >= max pc range - use the slope at pc=%d\n",
pc, pc_temp_ocv->percent[0]);
row1 = 0;
row2 = 1;
} else if (pc <= pc_temp_ocv->percent[rows - 1]) {
pr_debug("pc %d is <= min pc range - use the slope at pc=%d\n",
pc, pc_temp_ocv->percent[rows - 1]);
row1 = rows - 2;
row2 = rows - 1;
} else {
for (i = 0; i < rows; i++) {
if (pc == pc_temp_ocv->percent[i]) {
row1 = i - 1;
row2 = i;
break;
}
if (pc > pc_temp_ocv->percent[i]) {
row1 = i - 1;
row2 = i;
break;
}
}
}
if (batt_temp < pc_temp_ocv->temp[0] * DEGC_SCALE)
batt_temp = pc_temp_ocv->temp[0] * DEGC_SCALE;
if (batt_temp > pc_temp_ocv->temp[cols - 1] * DEGC_SCALE)
batt_temp = pc_temp_ocv->temp[cols - 1] * DEGC_SCALE;
for (i = 0; i < cols; i++)
if (batt_temp <= pc_temp_ocv->temp[i] * DEGC_SCALE)
break;
if (batt_temp == pc_temp_ocv->temp[i] * DEGC_SCALE) {
slope = (pc_temp_ocv->ocv[row1][i] -
pc_temp_ocv->ocv[row2][i]);
if (slope <= 0) {
pr_warn("Slope=%d for pc=%d, using 1\n", slope, pc);
slope = 1;
}
slope *= 1000;
slope /= (pc_temp_ocv->percent[row1] -
pc_temp_ocv->percent[row2]);
return slope;
}
ocvrow1 = linear_interpolate(
pc_temp_ocv->ocv[row1][i - 1],
pc_temp_ocv->temp[i - 1] * DEGC_SCALE,
pc_temp_ocv->ocv[row1][i],
pc_temp_ocv->temp[i] * DEGC_SCALE,
batt_temp);
ocvrow2 = linear_interpolate(
pc_temp_ocv->ocv[row2][i - 1],
pc_temp_ocv->temp[i - 1] * DEGC_SCALE,
pc_temp_ocv->ocv[row2][i],
pc_temp_ocv->temp[i] * DEGC_SCALE,
batt_temp);
slope = (ocvrow1 - ocvrow2);
if (slope <= 0) {
pr_warn("Slope=%d for pc=%d, using 1\n", slope, pc);
slope = 1;
}
slope *= 1000;
slope /= (pc_temp_ocv->percent[row1] - pc_temp_ocv->percent[row2]);
return slope;
}
int interpolate_acc(struct ibat_temp_acc_lut *ibat_acc_lut,
int batt_temp, int ibat)
{
int i, accrow1, accrow2, rows, cols;
int row1 = 0;
int row2 = 0;
int acc;
rows = ibat_acc_lut->rows;
cols = ibat_acc_lut->cols;
if (ibat > ibat_acc_lut->ibat[rows - 1]) {
pr_debug("ibatt(%d) > max range(%d)\n", ibat,
ibat_acc_lut->ibat[rows - 1]);
row1 = rows - 1;
row2 = rows - 2;
} else if (ibat < ibat_acc_lut->ibat[0]) {
pr_debug("ibatt(%d) < max range(%d)\n", ibat,
ibat_acc_lut->ibat[0]);
row1 = 0;
row2 = 0;
} else {
for (i = 0; i < rows; i++) {
if (ibat == ibat_acc_lut->ibat[i]) {
row1 = i;
row2 = i;
break;
}
if (ibat < ibat_acc_lut->ibat[i]) {
row1 = i;
row2 = i - 1;
break;
}
}
}
if (batt_temp < ibat_acc_lut->temp[0] * DEGC_SCALE)
batt_temp = ibat_acc_lut->temp[0] * DEGC_SCALE;
if (batt_temp > ibat_acc_lut->temp[cols - 1] * DEGC_SCALE)
batt_temp = ibat_acc_lut->temp[cols - 1] * DEGC_SCALE;
for (i = 0; i < cols; i++)
if (batt_temp <= ibat_acc_lut->temp[i] * DEGC_SCALE)
break;
if (batt_temp == (ibat_acc_lut->temp[i] * DEGC_SCALE)) {
acc = linear_interpolate(
ibat_acc_lut->acc[row1][i],
ibat_acc_lut->ibat[row1],
ibat_acc_lut->acc[row2][i],
ibat_acc_lut->ibat[row2],
ibat);
return acc;
}
accrow1 = linear_interpolate(
ibat_acc_lut->acc[row1][i - 1],
ibat_acc_lut->temp[i - 1] * DEGC_SCALE,
ibat_acc_lut->acc[row1][i],
ibat_acc_lut->temp[i] * DEGC_SCALE,
batt_temp);
accrow2 = linear_interpolate(
ibat_acc_lut->acc[row2][i - 1],
ibat_acc_lut->temp[i - 1] * DEGC_SCALE,
ibat_acc_lut->acc[row2][i],
ibat_acc_lut->temp[i] * DEGC_SCALE,
batt_temp);
acc = linear_interpolate(accrow1,
ibat_acc_lut->ibat[row1],
accrow2,
ibat_acc_lut->ibat[row2],
ibat);
if (acc < 0)
acc = 0;
return acc;
}

3683
drivers/power/supply/qcom/qpnp-linear-charger.c Normal file
View file

File diff suppressed because it is too large Load diff

4654
drivers/power/supply/qcom/qpnp-vm-bms.c Normal file
View file

File diff suppressed because it is too large Load diff

5444
drivers/power/supply/qcom/smb1360-charger-fg.c Normal file
View file

File diff suppressed because it is too large Load diff

14
drivers/power/supply/qcom/smb1398-charger.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "SMB1398: %s: " fmt, __func__
@ -1715,6 +1715,10 @@ static void smb1398_status_change_work(struct work_struct *work)
chip->usb_present = !!pval.intval;
if (!chip->usb_present) /* USB has been removed */
smb1398_toggle_uvlo(chip);
pval.intval = 1;
if (is_cps_available(chip))
power_supply_set_property(chip->div2_cp_slave_psy,
POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER, &pval);
}
rc = power_supply_get_property(chip->usb_psy,
@ -2274,6 +2278,7 @@ static enum power_supply_property div2_cp_slave_props[] = {
POWER_SUPPLY_PROP_CP_ENABLE,
POWER_SUPPLY_PROP_INPUT_CURRENT_MAX,
POWER_SUPPLY_PROP_CURRENT_CAPABILITY,
POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER,
};
static int div2_cp_slave_get_prop(struct power_supply *psy,
@ -2297,6 +2302,9 @@ static int div2_cp_slave_get_prop(struct power_supply *psy,
case POWER_SUPPLY_PROP_CURRENT_CAPABILITY:
pval->intval = (int)chip->current_capability;
break;
case POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER:
pval->intval = 0;
break;
default:
dev_err(chip->dev, "read div2_cp_slave property %d is not supported\n",
prop);
@ -2329,6 +2337,10 @@ static int div2_cp_slave_set_prop(struct power_supply *psy,
return rc;
chip->current_capability = mode;
break;
case POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER:
/* use this case to toggle UVLO */
rc = smb1398_toggle_uvlo(chip);
break;
default:
dev_err(chip->dev, "write div2_cp_slave property %d is not supported\n",
prop);

40
drivers/soc/qcom/memory_dump_v2.c
View file

@ -82,6 +82,7 @@ struct msm_memory_dump {
};
static struct msm_memory_dump memdump;
static struct msm_mem_dump_vaddr_tbl vaddr_tbl;
/**
* update_reg_dump_table - update the register dump table
@ -699,6 +700,28 @@ int msm_dump_data_register_nominidump(enum msm_dump_table_ids id,
}
EXPORT_SYMBOL(msm_dump_data_register_nominidump);
struct dump_vaddr_entry *get_msm_dump_ptr(enum msm_dump_data_ids id)
{
int i;
if (!vaddr_tbl.entries)
return NULL;
if (id > MSM_DUMP_DATA_MAX)
return NULL;
for (i = 0; i < vaddr_tbl.num_node; i++) {
if (vaddr_tbl.entries[i].id == id)
break;
}
if (i == vaddr_tbl.num_node)
return NULL;
return &vaddr_tbl.entries[i];
}
EXPORT_SYMBOL(get_msm_dump_ptr);
#define MSM_DUMP_TOTAL_SIZE_OFFSET 0x724
static int init_memory_dump(void *dump_vaddr, phys_addr_t phys_addr,
size_t size)
@ -787,6 +810,14 @@ static int mem_dump_alloc(struct platform_device *pdev)
uint32_t ns_vmids[] = {VMID_HLOS};
uint32_t ns_vm_perms[] = {PERM_READ | PERM_WRITE};
u64 shm_bridge_handle;
int i = 0;
vaddr_tbl.num_node = of_get_child_count(node);
vaddr_tbl.entries = devm_kcalloc(&pdev->dev, vaddr_tbl.num_node,
sizeof(struct dump_vaddr_entry),
GFP_KERNEL);
if (!vaddr_tbl.entries)
dev_err(&pdev->dev, "Unable to allocate mem for ptr addr\n");
total_size = size = ret = no_of_nodes = 0;
/* For dump table registration with IMEM */
@ -862,9 +893,16 @@ static int mem_dump_alloc(struct platform_device *pdev)
dump_entry.addr = phys_addr;
ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
&dump_entry);
if (ret)
if (ret) {
dev_err(&pdev->dev, "Data dump setup failed, id = %d\n",
id);
} else if (vaddr_tbl.entries) {
vaddr_tbl.entries[i].id = id;
vaddr_tbl.entries[i].dump_vaddr =
dump_vaddr + MSM_DUMP_DATA_SIZE;
vaddr_tbl.entries[i].dump_data_vaddr = dump_data;
i++;
}
md_entry.phys_addr = dump_data->addr;
md_entry.virt_addr = (uintptr_t)dump_vaddr + MSM_DUMP_DATA_SIZE;

5
drivers/soc/qcom/qdss_bridge.c
View file

@ -151,7 +151,8 @@ static int qdss_check_entry(struct qdss_bridge_drvdata *drvdata)
int ret = 0;
list_for_each_entry(entry, &drvdata->buf_tbl, link) {
if (atomic_read(&entry->available) == 0) {
if (atomic_read(&entry->available) == 0
&& atomic_read(&entry->used) == 1) {
ret = 1;
return ret;
}
@ -199,6 +200,7 @@ static void qdss_buf_tbl_remove(struct qdss_bridge_drvdata *drvdata,
if (entry->buf != buf)
continue;
atomic_set(&entry->available, 1);
atomic_set(&entry->used, 0);
spin_unlock_bh(&drvdata->lock);
return;
}
@ -382,6 +384,7 @@ static int usb_write(struct qdss_bridge_drvdata *drvdata,
entry->usb_req->buf = buf;
entry->usb_req->length = len;
atomic_set(&entry->used, 1);
ret = usb_qdss_write(drvdata->usb_ch, entry->usb_req);
return ret;

3
drivers/soc/qcom/qdss_bridge.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _QDSS_BRIDGE_H
@ -11,6 +11,7 @@ struct qdss_buf_tbl_lst {
unsigned char *buf;
struct qdss_request *usb_req;
atomic_t available;
atomic_t used;
};
struct qdss_mhi_buf_tbl_t {

14
drivers/thermal/qcom/qmi_sensors.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2018-2020,2021 The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "%s:%s " fmt, KBUILD_MODNAME, __func__
@ -124,7 +124,7 @@ static char sensor_clients[QMI_TS_MAX_NR][QMI_CLIENT_NAME_LENGTH] = {
static int32_t encode_qmi(int32_t val)
{
uint32_t shift = 0, local_val = 0;
int32_t temp_val = 0;
unsigned long temp_val = 0;
if (val == INT_MAX || val == INT_MIN)
return 0;
@ -134,8 +134,7 @@ static int32_t encode_qmi(int32_t val)
temp_val *= -1;
local_val |= 1 << QMI_FL_SIGN_BIT;
}
shift = find_last_bit((const unsigned long *)&temp_val,
sizeof(temp_val) * 8);
shift = find_last_bit(&temp_val, sizeof(temp_val) * 8);
local_val |= ((shift + 127) << QMI_MANTISSA_MSB);
temp_val &= ~(1 << shift);
@ -279,6 +278,13 @@ static int qmi_ts_request(struct qmi_sensor *qmi_sens,
qmi_sens->low_thresh != INT_MIN;
req.temp_threshold_low =
encode_qmi(qmi_sens->low_thresh);
pr_debug("Sensor:%s set high_trip:%d, low_trip:%d, high_valid:%d, low_valid:%d\n",
qmi_sens->qmi_name,
qmi_sens->high_thresh,
qmi_sens->low_thresh,
req.temp_threshold_high_valid,
req.temp_threshold_low_valid);
}
mutex_lock(&ts->mutex);

8
drivers/thermal/qpnp-adc-tm.c
View file

@ -2330,11 +2330,11 @@ static int qpnp_adc_tm_measure_ref_points(struct qpnp_adc_tm_chip *chip)
int ret;
struct qpnp_adc_drv *adc = chip->adc;
ret = iio_read_channel_processed(chip->ref_1250v, &read_1);
ret = iio_read_channel_raw(chip->ref_1250v, &read_1);
if (ret < 0)
goto err;
ret = iio_read_channel_processed(chip->ref_625mv, &read_2);
ret = iio_read_channel_raw(chip->ref_625mv, &read_2);
if (ret < 0)
goto err;
@ -2356,11 +2356,11 @@ static int qpnp_adc_tm_measure_ref_points(struct qpnp_adc_tm_chip *chip)
read_1 = 0;
read_2 = 0;
ret = iio_read_channel_processed(chip->ref_vdd, &read_1);
ret = iio_read_channel_raw(chip->ref_vdd, &read_1);
if (ret < 0)
goto err;
ret = iio_read_channel_processed(chip->ref_gnd, &read_2);
ret = iio_read_channel_raw(chip->ref_gnd, &read_2);
if (ret < 0)
goto err;

7
drivers/tty/tty_io.c
View file

@ -2751,10 +2751,14 @@ void __do_SAK(struct tty_struct *tty)
struct task_struct *g, *p;
struct pid *session;
int i;
unsigned long flags;
if (!tty)
return;
session = tty->session;
spin_lock_irqsave(&tty->ctrl_lock, flags);
session = get_pid(tty->session);
spin_unlock_irqrestore(&tty->ctrl_lock, flags);
tty_ldisc_flush(tty);
@ -2786,6 +2790,7 @@ void __do_SAK(struct tty_struct *tty)
task_unlock(p);
} while_each_thread(g, p);
read_unlock(&tasklist_lock);
put_pid(session);
#endif
}

44
drivers/tty/tty_jobctrl.c
View file

@ -103,8 +103,8 @@ static void __proc_set_tty(struct tty_struct *tty)
put_pid(tty->session);
put_pid(tty->pgrp);
tty->pgrp = get_pid(task_pgrp(current));
spin_unlock_irqrestore(&tty->ctrl_lock, flags);
tty->session = get_pid(task_session(current));
spin_unlock_irqrestore(&tty->ctrl_lock, flags);
if (current->signal->tty) {
tty_debug(tty, "current tty %s not NULL!!\n",
current->signal->tty->name);
@ -293,20 +293,23 @@ void disassociate_ctty(int on_exit)
spin_lock_irq(&current->sighand->siglock);
put_pid(current->signal->tty_old_pgrp);
current->signal->tty_old_pgrp = NULL;
tty = tty_kref_get(current->signal->tty);
spin_unlock_irq(&current->sighand->siglock);
if (tty) {
unsigned long flags;
tty_lock(tty);
spin_lock_irqsave(&tty->ctrl_lock, flags);
put_pid(tty->session);
put_pid(tty->pgrp);
tty->session = NULL;
tty->pgrp = NULL;
spin_unlock_irqrestore(&tty->ctrl_lock, flags);
tty_unlock(tty);
tty_kref_put(tty);
}
spin_unlock_irq(&current->sighand->siglock);
/* Now clear signal->tty under the lock */
read_lock(&tasklist_lock);
session_clear_tty(task_session(current));
@ -477,14 +480,19 @@ static int tiocspgrp(struct tty_struct *tty, struct tty_struct *real_tty, pid_t
return -ENOTTY;
if (retval)
return retval;
if (!current->signal->tty ||
(current->signal->tty != real_tty) ||
(real_tty->session != task_session(current)))
return -ENOTTY;
if (get_user(pgrp_nr, p))
return -EFAULT;
if (pgrp_nr < 0)
return -EINVAL;
spin_lock_irq(&real_tty->ctrl_lock);
if (!current->signal->tty ||
(current->signal->tty != real_tty) ||
(real_tty->session != task_session(current))) {
retval = -ENOTTY;
goto out_unlock_ctrl;
}
rcu_read_lock();
pgrp = find_vpid(pgrp_nr);
retval = -ESRCH;
@ -494,12 +502,12 @@ static int tiocspgrp(struct tty_struct *tty, struct tty_struct *real_tty, pid_t
if (session_of_pgrp(pgrp) != task_session(current))
goto out_unlock;
retval = 0;
spin_lock_irq(&real_tty->ctrl_lock);
put_pid(real_tty->pgrp);
real_tty->pgrp = get_pid(pgrp);
spin_unlock_irq(&real_tty->ctrl_lock);
out_unlock:
rcu_read_unlock();
out_unlock_ctrl:
spin_unlock_irq(&real_tty->ctrl_lock);
return retval;
}
@ -511,20 +519,30 @@ static int tiocspgrp(struct tty_struct *tty, struct tty_struct *real_tty, pid_t
*
* Obtain the session id of the tty. If there is no session
* return an error.
*
* Locking: none. Reference to current->signal->tty is safe.
*/
static int tiocgsid(struct tty_struct *tty, struct tty_struct *real_tty, pid_t __user *p)
{
unsigned long flags;
pid_t sid;
/*
* (tty == real_tty) is a cheap way of
* testing if the tty is NOT a master pty.
*/
if (tty == real_tty && current->signal->tty != real_tty)
return -ENOTTY;
spin_lock_irqsave(&real_tty->ctrl_lock, flags);
if (!real_tty->session)
return -ENOTTY;
return put_user(pid_vnr(real_tty->session), p);
goto err;
sid = pid_vnr(real_tty->session);
spin_unlock_irqrestore(&real_tty->ctrl_lock, flags);
return put_user(sid, p);
err:
spin_unlock_irqrestore(&real_tty->ctrl_lock, flags);
return -ENOTTY;
}
/*

2
drivers/usb/dwc3/dwc3-msm.c
View file

@ -2579,7 +2579,7 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc, bool enable_wakeup)
dbg_event(0xFF, "pend evt", 0);
/* disable power event irq, hs and ss phy irq is used as wake up src */
disable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq);
disable_irq_nosync(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq);
dwc3_set_phy_speed_flags(mdwc);
/* Suspend HS PHY */

8
drivers/usb/gadget/function/f_uvc.c
View file

@ -821,8 +821,8 @@ static struct usb_function_instance *uvc_alloc_inst(void)
cd->wObjectiveFocalLengthMax = cpu_to_le16(0);
cd->wOcularFocalLength = cpu_to_le16(0);
cd->bControlSize = 3;
cd->bmControls[0] = 46;
cd->bmControls[1] = 2;
cd->bmControls[0] = 62;
cd->bmControls[1] = 126;
cd->bmControls[2] = 10;
pd = &opts->uvc_processing;
@ -833,8 +833,8 @@ static struct usb_function_instance *uvc_alloc_inst(void)
pd->bSourceID = 1;
pd->wMaxMultiplier = cpu_to_le16(16*1024);
pd->bControlSize = 3;
pd->bmControls[0] = 90;
pd->bmControls[1] = 20;
pd->bmControls[0] = 91;
pd->bmControls[1] = 23;
pd->bmControls[2] = 4;
pd->iProcessing = 0;
pd->bmVideoStandards = 0;

4
include/linux/diagchar.h
View file

@ -143,7 +143,7 @@
* a new RANGE of SSIDs to the msg_mask_tbl.
*/
#define MSG_MASK_TBL_CNT 27
#define APPS_EVENT_LAST_ID 0xCFA
#define APPS_EVENT_LAST_ID 0xCFE
#define MSG_SSID_0 0
#define MSG_SSID_0_LAST 134
@ -950,7 +950,7 @@ static const uint32_t msg_bld_masks_26[] = {
/* LOG CODES */
static const uint32_t log_code_last_tbl[] = {
0x0, /* EQUIP ID 0 */
0x1D5E, /* EQUIP ID 1 */
0x1D86, /* EQUIP ID 1 */
0x0, /* EQUIP ID 2 */
0x0, /* EQUIP ID 3 */
0x4910, /* EQUIP ID 4 */

29
include/linux/mm.h
View file

@ -1498,22 +1498,13 @@ int generic_access_phys(struct vm_area_struct *vma, unsigned long addr,
#ifdef CONFIG_SPECULATIVE_PAGE_FAULT
static inline void vm_write_begin(struct vm_area_struct *vma)
{
write_seqcount_begin(&vma->vm_sequence);
}
static inline void vm_write_begin_nested(struct vm_area_struct *vma,
int subclass)
{
write_seqcount_begin_nested(&vma->vm_sequence, subclass);
}
static inline void vm_write_end(struct vm_area_struct *vma)
{
write_seqcount_end(&vma->vm_sequence);
}
static inline void vm_raw_write_begin(struct vm_area_struct *vma)
{
/*
* The reads never spins and preemption
* disablement is not required.
*/
raw_write_seqcount_begin(&vma->vm_sequence);
}
static inline void vm_raw_write_end(struct vm_area_struct *vma)
static inline void vm_write_end(struct vm_area_struct *vma)
{
raw_write_seqcount_end(&vma->vm_sequence);
}
@ -1521,19 +1512,9 @@ static inline void vm_raw_write_end(struct vm_area_struct *vma)
static inline void vm_write_begin(struct vm_area_struct *vma)
{
}
static inline void vm_write_begin_nested(struct vm_area_struct *vma,
int subclass)
{
}
static inline void vm_write_end(struct vm_area_struct *vma)
{
}
static inline void vm_raw_write_begin(struct vm_area_struct *vma)
{
}
static inline void vm_raw_write_end(struct vm_area_struct *vma)
{
}
#endif /* CONFIG_SPECULATIVE_PAGE_FAULT */
extern void truncate_pagecache(struct inode *inode, loff_t new);

4
include/linux/tty.h
View file

@ -306,6 +306,10 @@ struct tty_struct {
struct termiox *termiox; /* May be NULL for unsupported */
char name[64];
struct pid *pgrp; /* Protected by ctrl lock */
/*
* Writes protected by both ctrl lock and legacy mutex, readers must use
* at least one of them.
*/
struct pid *session;
unsigned long flags;
int count;

16
include/soc/qcom/memory_dump.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012, 2014-2017, 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2012, 2014-2017, 2019, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef __MSM_MEMORY_DUMP_H
@ -79,6 +79,8 @@ enum msm_dump_data_ids {
MSM_DUMP_DATA_TMC_ETF = 0xF0,
MSM_DUMP_DATA_TMC_ETF_SWAO = 0xF1,
MSM_DUMP_DATA_TMC_REG = 0x100,
MSM_DUMP_DATA_TMC_ETR_REG = 0x100,
MSM_DUMP_DATA_TMC_ETF_REG = 0x101,
MSM_DUMP_DATA_TMC_ETF_SWAO_REG = 0x102,
MSM_DUMP_DATA_LOG_BUF = 0x110,
MSM_DUMP_DATA_LOG_BUF_FIRST_IDX = 0x111,
@ -113,11 +115,23 @@ struct msm_dump_entry {
uint64_t addr;
};
struct dump_vaddr_entry {
uint32_t id;
void *dump_vaddr;
struct msm_dump_data *dump_data_vaddr;
};
struct msm_mem_dump_vaddr_tbl {
uint8_t num_node;
struct dump_vaddr_entry *entries;
};
#ifdef CONFIG_QCOM_MEMORY_DUMP_V2
extern int msm_dump_data_register(enum msm_dump_table_ids id,
struct msm_dump_entry *entry);
extern int msm_dump_data_register_nominidump(enum msm_dump_table_ids id,
struct msm_dump_entry *entry);
extern struct dump_vaddr_entry *get_msm_dump_ptr(enum msm_dump_data_ids id);
#else
static inline int msm_dump_data_register(enum msm_dump_table_ids id,
struct msm_dump_entry *entry)

38
mm/mmap.c
View file

@ -735,29 +735,9 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
long adjust_next = 0;
int remove_next = 0;
/*
* Why using vm_raw_write*() functions here to avoid lockdep's warning ?
*
* Locked is complaining about a theoretical lock dependency, involving
* 3 locks:
* mapping->i_mmap_rwsem --> vma->vm_sequence --> fs_reclaim
*
* Here are the major path leading to this dependency :
* 1. __vma_adjust() mmap_sem -> vm_sequence -> i_mmap_rwsem
* 2. move_vmap() mmap_sem -> vm_sequence -> fs_reclaim
* 3. __alloc_pages_nodemask() fs_reclaim -> i_mmap_rwsem
* 4. unmap_mapping_range() i_mmap_rwsem -> vm_sequence
*
* So there is no way to solve this easily, especially because in
* unmap_mapping_range() the i_mmap_rwsem is grab while the impacted
* VMAs are not yet known.
* However, the way the vm_seq is used is guarantying that we will
* never block on it since we just check for its value and never wait
* for it to move, see vma_has_changed() and handle_speculative_fault().
*/
vm_raw_write_begin(vma);
vm_write_begin(vma);
if (next)
vm_raw_write_begin(next);
vm_write_begin(next);
if (next && !insert) {
struct vm_area_struct *exporter = NULL, *importer = NULL;
@ -841,8 +821,8 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
error = anon_vma_clone(importer, exporter);
if (error) {
if (next && next != vma)
vm_raw_write_end(next);
vm_raw_write_end(vma);
vm_write_end(next);
vm_write_end(vma);
return error;
}
}
@ -971,7 +951,7 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
if (next->anon_vma)
anon_vma_merge(vma, next);
mm->map_count--;
vm_raw_write_end(next);
vm_write_end(next);
put_vma(next);
/*
* In mprotect's case 6 (see comments on vma_merge),
@ -987,7 +967,7 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
*/
next = vma->vm_next;
if (next)
vm_raw_write_begin(next);
vm_write_begin(next);
} else {
/*
* For the scope of the comment "next" and
@ -1035,9 +1015,9 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
uprobe_mmap(insert);
if (next && next != vma)
vm_raw_write_end(next);
vm_write_end(next);
if (!keep_locked)
vm_raw_write_end(vma);
vm_write_end(vma);
validate_mm(mm);
@ -3348,7 +3328,7 @@ struct vm_area_struct *copy_vma(struct vm_area_struct **vmap,
* that we protect it right now, and let the caller unprotect
* it once the move is done.
*/
vm_raw_write_begin(new_vma);
vm_write_begin(new_vma);
vma_link(mm, new_vma, prev, rb_link, rb_parent);
*need_rmap_locks = false;
}

8
mm/mremap.c
View file

@ -300,7 +300,7 @@ static unsigned long move_vma(struct vm_area_struct *vma,
* to be mapped in our back while we are copying the PTEs.
*/
if (vma != new_vma)
vm_raw_write_begin(vma);
vm_write_begin(vma);
moved_len = move_page_tables(vma, old_addr, new_vma, new_addr, old_len,
need_rmap_locks);
@ -319,7 +319,7 @@ static unsigned long move_vma(struct vm_area_struct *vma,
move_page_tables(new_vma, new_addr, vma, old_addr, moved_len,
true);
if (vma != new_vma)
vm_raw_write_end(vma);
vm_write_end(vma);
vma = new_vma;
old_len = new_len;
old_addr = new_addr;
@ -329,9 +329,9 @@ static unsigned long move_vma(struct vm_area_struct *vma,
arch_remap(mm, old_addr, old_addr + old_len,
new_addr, new_addr + new_len);
if (vma != new_vma)
vm_raw_write_end(vma);
vm_write_end(vma);
}
vm_raw_write_end(new_vma);
vm_write_end(new_vma);
/* Conceal VM_ACCOUNT so old reservation is not undone */
if (vm_flags & VM_ACCOUNT) {

5
net/qrtr/qrtr.c
View file

@ -1731,6 +1731,11 @@ static int qrtr_recvmsg(struct socket *sock, struct msghdr *msg,
rc = copied;
if (addr) {
/* There is an anonymous 2-byte hole after sq_family,
* make sure to clear it.
*/
memset(addr, 0, sizeof(*addr));
addr->sq_family = AF_QIPCRTR;
addr->sq_node = cb->src_node;
addr->sq_port = cb->src_port;

2
net/qrtr/smd.c
View file

@ -24,7 +24,7 @@ static int qcom_smd_qrtr_callback(struct rpmsg_device *rpdev,
int rc;
if (!qdev) {
pr_err("%s:Not ready\n", __func__);
pr_err_ratelimited("%s:Not ready\n", __func__);
return -EAGAIN;
}