[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Marc St-Jean
Ralf Baechle
parent
35832e26f9
commit
9267a30d1d
10 changed files with 179 additions and 2 deletions
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@ -250,6 +250,7 @@ config MIPS_SIM
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select DMA_NONCOHERENT
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select SYS_HAS_EARLY_PRINTK
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select IRQ_CPU
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select BOOT_RAW
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_EARLY_PRINTK
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@ -333,6 +334,27 @@ config MACH_VR41XX
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select SYS_HAS_CPU_VR41XX
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config PMC_MSP
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bool "PMC-Sierra MSP chipsets"
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depends on EXPERIMENTAL
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select DMA_NONCOHERENT
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select SWAP_IO_SPACE
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select NO_EXCEPT_FILL
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select BOOT_RAW
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_KGDB
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select IRQ_CPU
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select SERIAL_8250
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select SERIAL_8250_CONSOLE
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help
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This adds support for the PMC-Sierra family of Multi-Service
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Processor System-On-A-Chips. These parts include a number
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of integrated peripherals, interfaces and DSPs in addition to
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a variety of MIPS cores.
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config PMC_YOSEMITE
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bool "PMC-Sierra Yosemite eval board"
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select DMA_COHERENT
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@ -706,6 +728,9 @@ config ARC
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config ARCH_MAY_HAVE_PC_FDC
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bool
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config BOOT_RAW
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bool
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config DMA_COHERENT
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bool
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@ -812,6 +837,12 @@ config IRQ_CPU_RM7K
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config IRQ_CPU_RM9K
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bool
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config IRQ_MSP_SLP
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bool
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config IRQ_MSP_CIC
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bool
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config IRQ_MV64340
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bool
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@ -825,6 +856,9 @@ config MIPS_BOARDS_GEN
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config PCI_GT64XXX_PCI0
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bool
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config NO_EXCEPT_FILL
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bool
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config MIPS_TX3927
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bool
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select HAS_TXX9_SERIAL
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@ -886,6 +920,7 @@ config MIPS_L1_CACHE_SHIFT
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int
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default "4" if MACH_DECSTATION || SNI_RM
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default "7" if SGI_IP27
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default "4" if PMC_MSP4200_EVAL
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default "5"
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config HAVE_STD_PC_SERIAL_PORT
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@ -342,6 +342,14 @@ core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
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cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
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load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
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#
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# PMC-Sierra MSP SOCs
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#
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core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
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cflags-$(CONFIG_PMC_MSP) += -Iinclude/asm-mips/pmc-sierra/msp71xx \
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-mno-branch-likely
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load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
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#
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# PMC-Sierra Yosemite
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#
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@ -595,7 +603,8 @@ JIFFIES = jiffies_64
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endif
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AFLAGS += $(cflags-y)
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CFLAGS += $(cflags-y)
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CFLAGS += $(cflags-y) \
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-D"VMLINUX_LOAD_ADDRESS=$(load-y)"
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LDFLAGS += -m $(ld-emul)
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@ -186,9 +186,29 @@ static inline void check_wait(void)
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}
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}
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static inline void check_errata(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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switch (c->cputype) {
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case CPU_34K:
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/*
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* Erratum "RPS May Cause Incorrect Instruction Execution"
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* This code only handles VPE0, any SMP/SMTC/RTOS code
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* making use of VPE1 will be responsable for that VPE.
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*/
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if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
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write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
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break;
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default:
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break;
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}
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}
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void __init check_bugs32(void)
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{
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check_wait();
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check_errata();
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}
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/*
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@ -16,6 +16,7 @@
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/irqflags.h>
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@ -129,16 +130,18 @@
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#endif
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.endm
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#ifndef CONFIG_NO_EXCEPT_FILL
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/*
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* Reserved space for exception handlers.
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* Necessary for machines which link their kernels at KSEG0.
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*/
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.fill 0x400
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#endif
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EXPORT(stext) # used for profiling
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EXPORT(_stext)
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#ifndef CONFIG_MIPS_SIM
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#ifdef CONFIG_BOOT_RAW
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/*
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* Give us a fighting chance of running if execution beings at the
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* kernel load address. This is needed because this platform does
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@ -69,6 +69,7 @@ extern asmlinkage void handle_reserved(void);
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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struct mips_fpu_struct *ctx, int has_fpu);
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void (*board_watchpoint_handler)(struct pt_regs *regs);
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void (*board_be_init)(void);
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int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
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void (*board_nmi_handler_setup)(void);
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@ -833,6 +834,11 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
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asmlinkage void do_watch(struct pt_regs *regs)
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{
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if (board_watchpoint_handler) {
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(*board_watchpoint_handler)(regs);
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return;
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}
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/*
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* We use the watch exception where available to detect stack
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* overflows.
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@ -1,3 +1,49 @@
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choice
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prompt "PMC-Sierra MSP SOC type"
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depends on PMC_MSP
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config PMC_MSP4200_EVAL
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bool "PMC-Sierra MSP4200 Eval Board"
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select IRQ_MSP_SLP
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select HW_HAS_PCI
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config PMC_MSP4200_GW
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bool "PMC-Sierra MSP4200 VoIP Gateway"
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select IRQ_MSP_SLP
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select HW_HAS_PCI
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config PMC_MSP7120_EVAL
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bool "PMC-Sierra MSP7120 Eval Board"
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select SYS_SUPPORTS_MULTITHREADING
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select IRQ_MSP_CIC
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select HW_HAS_PCI
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config PMC_MSP7120_GW
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bool "PMC-Sierra MSP7120 Residential Gateway"
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select SYS_SUPPORTS_MULTITHREADING
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select IRQ_MSP_CIC
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select HW_HAS_PCI
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config PMC_MSP7120_FPGA
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bool "PMC-Sierra MSP7120 FPGA"
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select SYS_SUPPORTS_MULTITHREADING
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select IRQ_MSP_CIC
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select HW_HAS_PCI
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endchoice
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menu "Options for PMC-Sierra MSP chipsets"
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depends on PMC_MSP
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config PMC_MSP_EMBEDDED_ROOTFS
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bool "Root filesystem embedded in kernel image"
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select MTD
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select MTD_BLOCK
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select MTD_PMC_MSP_RAMROOT
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select MTD_RAM
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endmenu
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config HYPERTRANSPORT
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bool "Hypertransport Support for PMC-Sierra Yosemite"
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depends on PMC_YOSEMITE
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@ -213,6 +213,18 @@
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#define MACH_GROUP_LEMOTE 27
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#define MACH_LEMOTE_FULONG 0
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/*
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* Valid machtype for group PMC-MSP
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*/
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#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */
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#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
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#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
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#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
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#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
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#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
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#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
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#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
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#define CL_SIZE COMMAND_LINE_SIZE
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const char *get_system_type(void);
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@ -109,6 +109,7 @@
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* Definitions for 7:0 on legacy processors
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*/
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#define PRID_REV_MASK 0x00ff
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#define PRID_REV_TX4927 0x0022
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#define PRID_REV_TX4937 0x0030
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@ -125,6 +126,7 @@
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#define PRID_REV_VR4122 0x0070
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#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
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#define PRID_REV_VR4130 0x0080
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#define PRID_REV_34K_V1_0_2 0x0022
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/*
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* Older processors used to encode processor version and revision in two
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@ -15,6 +15,7 @@
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#include <linux/linkage.h>
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#include <asm/hazards.h>
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#include <asm/war.h>
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/*
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* The following macros are especially useful for __asm__
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@ -537,6 +538,9 @@
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#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
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#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
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/*
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* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
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*/
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@ -1298,10 +1302,39 @@ static inline void tlb_probe(void)
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static inline void tlb_read(void)
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{
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#if MIPS34K_MISSED_ITLB_WAR
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int res = 0;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" .word 0x41610001 # dvpe $1 \n"
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" move %0, $1 \n"
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" ehb \n"
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" .set pop \n"
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: "=r" (res));
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instruction_hazard();
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#endif
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__asm__ __volatile__(
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".set noreorder\n\t"
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"tlbr\n\t"
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".set reorder");
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#if MIPS34K_MISSED_ITLB_WAR
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if ((res & _ULCAST_(1)))
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" .word 0x41600021 # evpe \n"
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" ehb \n"
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" .set pop \n");
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#endif
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}
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static inline void tlb_write_indexed(void)
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@ -197,6 +197,14 @@
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#define R10000_LLSC_WAR 1
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#endif
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/*
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* 34K core erratum: "Problems Executing the TLBR Instruction"
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*/
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#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
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defined(CONFIG_PMC_MSP7120_FPGA)
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#define MIPS34K_MISSED_ITLB_WAR 1
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#endif
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/*
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* Workarounds default to off
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*/
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@ -236,5 +244,8 @@
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#ifndef R10000_LLSC_WAR
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#define R10000_LLSC_WAR 0
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#endif
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#ifndef MIPS34K_MISSED_ITLB_WAR
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif
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#endif /* _ASM_WAR_H */
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