USB: langwell: USB Client driver memory handling
SRAM Memory handling for USB client function Signed-off-by: JiebingLi <jiebing.li@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
JiebingLi
Greg Kroah-Hartman
parent
3211cbc20b
commit
912c93d160
2 changed files with 115 additions and 10 deletions
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@ -2988,6 +2988,50 @@ static void gadget_release(struct device *_dev)
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}
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/* enable SRAM caching if SRAM detected */
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static void sram_init(struct langwell_udc *dev)
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{
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struct pci_dev *pdev = dev->pdev;
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dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
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dev->sram_addr = pci_resource_start(pdev, 1);
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dev->sram_size = pci_resource_len(pdev, 1);
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dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
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dev->sram_addr, dev->sram_size);
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dev->got_sram = 1;
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if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
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dev_warn(&dev->pdev->dev, "SRAM request failed\n");
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dev->got_sram = 0;
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} else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
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dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
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dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
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pci_release_region(pdev, 1);
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dev->got_sram = 0;
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}
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dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
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}
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/* release SRAM caching */
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static void sram_deinit(struct langwell_udc *dev)
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{
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struct pci_dev *pdev = dev->pdev;
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dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
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dma_release_declared_memory(&pdev->dev);
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pci_release_region(pdev, 1);
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dev->got_sram = 0;
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dev_info(&dev->pdev->dev, "release SRAM caching\n");
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dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
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}
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/* tear down the binding between this driver and the pci device */
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static void langwell_udc_remove(struct pci_dev *pdev)
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{
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@ -3000,19 +3044,25 @@ static void langwell_udc_remove(struct pci_dev *pdev)
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dev->done = &done;
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/* free memory allocated in probe */
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#ifndef OTG_TRANSCEIVER
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/* free dTD dma_pool and dQH */
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if (dev->dtd_pool)
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dma_pool_destroy(dev->dtd_pool);
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if (dev->ep_dqh)
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dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
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dev->ep_dqh, dev->ep_dqh_dma);
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/* release SRAM caching */
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if (dev->has_sram && dev->got_sram)
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sram_deinit(dev);
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#endif
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if (dev->status_req) {
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kfree(dev->status_req->req.buf);
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kfree(dev->status_req);
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}
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if (dev->ep_dqh)
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dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
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dev->ep_dqh, dev->ep_dqh_dma);
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kfree(dev->ep);
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/* diable IRQ handler */
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@ -3140,7 +3190,15 @@ static int langwell_udc_probe(struct pci_dev *pdev,
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goto error;
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}
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dev->has_sram = 1;
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dev->got_sram = 0;
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dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
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#ifndef OTG_TRANSCEIVER
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/* enable SRAM caching if detected */
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if (dev->has_sram && !dev->got_sram)
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sram_init(dev);
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dev_info(&dev->pdev->dev,
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"irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
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pdev->irq, resource, len, base);
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@ -3335,6 +3393,18 @@ static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
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/* save PCI state */
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pci_save_state(pdev);
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/* free dTD dma_pool and dQH */
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if (dev->dtd_pool)
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dma_pool_destroy(dev->dtd_pool);
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if (dev->ep_dqh)
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dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
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dev->ep_dqh, dev->ep_dqh_dma);
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/* release SRAM caching */
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if (dev->has_sram && dev->got_sram)
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sram_deinit(dev);
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/* set device power state */
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pci_set_power_state(pdev, PCI_D3hot);
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@ -3351,6 +3421,7 @@ static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
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static int langwell_udc_resume(struct pci_dev *pdev)
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{
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struct langwell_udc *dev = the_controller;
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size_t size;
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dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
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@ -3361,6 +3432,38 @@ static int langwell_udc_resume(struct pci_dev *pdev)
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/* set device D0 power state */
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pci_set_power_state(pdev, PCI_D0);
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/* enable SRAM caching if detected */
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if (dev->has_sram && !dev->got_sram)
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sram_init(dev);
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/* allocate device dQH memory */
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size = dev->ep_max * sizeof(struct langwell_dqh);
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dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size);
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if (size < DQH_ALIGNMENT)
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size = DQH_ALIGNMENT;
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else if ((size % DQH_ALIGNMENT) != 0) {
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size += DQH_ALIGNMENT + 1;
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size &= ~(DQH_ALIGNMENT - 1);
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}
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dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
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&dev->ep_dqh_dma, GFP_KERNEL);
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if (!dev->ep_dqh) {
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dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
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return -ENOMEM;
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}
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dev->ep_dqh_size = size;
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dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
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/* create dTD dma_pool resource */
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dev->dtd_pool = dma_pool_create("langwell_dtd",
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&dev->pdev->dev,
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sizeof(struct langwell_dtd),
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DTD_ALIGNMENT,
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DMA_BOUNDARY);
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if (!dev->dtd_pool)
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return -ENOMEM;
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/* restore PCI state */
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pci_restore_state(pdev);
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@ -18,11 +18,7 @@
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*/
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#include <linux/usb/langwell_udc.h>
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#if defined(CONFIG_USB_LANGWELL_OTG)
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#include <linux/usb/langwell_otg.h>
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#endif
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/*-------------------------------------------------------------------------*/
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@ -199,7 +195,9 @@ struct langwell_udc {
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vbus_active:1,
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suspended:1,
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stopped:1,
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lpm:1; /* LPM capability */
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lpm:1, /* LPM capability */
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has_sram:1, /* SRAM caching */
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got_sram:1;
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/* pci state used to access those endpoints */
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struct pci_dev *pdev;
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@ -225,6 +223,10 @@ struct langwell_udc {
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/* make sure release() is done */
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struct completion *done;
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/* for private SRAM caching */
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unsigned int sram_addr;
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unsigned int sram_size;
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/* device status data for get_status request */
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u16 dev_status;
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};
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