cpupower: Add support for new AMD family 0x17
Add support for new AMD family 0x17 - Add bit field changes to the msr_pstate structure - Add the new formula for the calculation of cof - Changed method to access to CpbDis Signed-off-by: Sherry Hurwitz <sherry.hurwitz@amd.com> Acked-by: Thomas Renninger <trenn@suse.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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3 changed files with 44 additions and 11 deletions
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@ -26,6 +26,15 @@ union msr_pstate {
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unsigned res3:21;
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unsigned en:1;
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} bits;
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struct {
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unsigned fid:8;
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unsigned did:6;
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unsigned vid:8;
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unsigned iddval:8;
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unsigned idddiv:2;
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unsigned res1:30;
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unsigned en:1;
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} fam17h_bits;
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unsigned long long val;
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};
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@ -35,6 +44,8 @@ static int get_did(int family, union msr_pstate pstate)
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if (family == 0x12)
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t = pstate.val & 0xf;
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else if (family == 0x17)
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t = pstate.fam17h_bits.did;
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else
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t = pstate.bits.did;
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@ -44,16 +55,20 @@ static int get_did(int family, union msr_pstate pstate)
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static int get_cof(int family, union msr_pstate pstate)
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{
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int t;
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int fid, did;
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int fid, did, cof;
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did = get_did(family, pstate);
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t = 0x10;
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fid = pstate.bits.fid;
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if (family == 0x11)
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t = 0x8;
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return (100 * (fid + t)) >> did;
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if (family == 0x17) {
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fid = pstate.fam17h_bits.fid;
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cof = 200 * fid / did;
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} else {
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t = 0x10;
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fid = pstate.bits.fid;
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if (family == 0x11)
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t = 0x8;
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cof = (100 * (fid + t)) >> did;
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}
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return cof;
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}
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/* Needs:
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@ -70,6 +70,8 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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#define CPUPOWER_CAP_IS_SNB 0x00000020
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#define CPUPOWER_CAP_INTEL_IDA 0x00000040
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#define CPUPOWER_AMD_CPBDIS 0x02000000
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#define MAX_HW_PSTATES 10
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struct cpupower_cpu_info {
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@ -2,11 +2,14 @@
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#include "helpers/helpers.h"
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#define MSR_AMD_HWCR 0xc0010015
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int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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int *states)
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{
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struct cpupower_cpu_info cpu_info;
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int ret;
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unsigned long long val;
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*support = *active = *states = 0;
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@ -16,9 +19,22 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
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*support = 1;
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ret = amd_pci_get_num_boost_states(active, states);
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if (ret)
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return ret;
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/* AMD Family 0x17 does not utilize PCI D18F4 like prior
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* families and has no fixed discrete boost states but
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* has Hardware determined variable increments instead.
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*/
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if (cpu_info.family == 0x17) {
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if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
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if (!(val & CPUPOWER_AMD_CPBDIS))
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*active = 1;
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}
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} else {
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ret = amd_pci_get_num_boost_states(active, states);
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if (ret)
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return ret;
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}
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} else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
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*support = *active = 1;
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return 0;
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