clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very complicated clocks, but is not really needed here. Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux + divider. This makes the code easier to understand. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai
Maxime Ripard
parent
3ca2377b6f
commit
8f2bf2ad96
1 changed files with 78 additions and 47 deletions
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@ -15,68 +15,99 @@
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of_address.h>
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#include "clk-factors.h"
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/**
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* sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks
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* MBUS rate is calculated as follows
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* rate = parent_rate / (m + 1);
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*/
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static void sun8i_a23_get_mbus_factors(struct factors_request *req)
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{
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u8 div;
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/*
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* These clocks can only divide, so we will never be able to
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* achieve frequencies higher than the parent frequency
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*/
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if (req->rate > req->parent_rate)
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req->rate = req->parent_rate;
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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if (div > 8)
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div = 8;
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req->rate = req->parent_rate / div;
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req->m = div - 1;
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}
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static struct clk_factors_config sun8i_a23_mbus_config = {
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.mshift = 0,
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.mwidth = 3,
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};
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static const struct factors_data sun8i_a23_mbus_data __initconst = {
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.enable = 31,
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.mux = 24,
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.muxmask = BIT(1) | BIT(0),
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.table = &sun8i_a23_mbus_config,
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.getter = sun8i_a23_get_mbus_factors,
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};
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#define SUN8I_MBUS_ENABLE 31
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#define SUN8I_MBUS_MUX_SHIFT 24
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#define SUN8I_MBUS_MUX_MASK 0x3
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#define SUN8I_MBUS_DIV_SHIFT 0
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#define SUN8I_MBUS_DIV_WIDTH 3
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#define SUN8I_MBUS_MAX_PARENTS 4
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static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
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static void __init sun8i_a23_mbus_setup(struct device_node *node)
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{
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struct clk *mbus;
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int num_parents = of_clk_get_parent_count(node);
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const char *parents[num_parents];
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const char *clk_name = node->name;
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struct resource res;
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struct clk_divider *div;
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struct clk_gate *gate;
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struct clk_mux *mux;
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struct clk *clk;
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void __iomem *reg;
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int err;
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reg = of_iomap(node, 0);
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a23-mbus-clk\n");
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pr_err("Could not get registers for sun8i-mbus-clk\n");
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return;
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}
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mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
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&sun8i_a23_mbus_lock, reg);
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto err_unmap;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto err_free_div;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_free_mux;
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of_property_read_string(node, "clock-output-names", &clk_name);
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of_clk_parent_fill(node, parents, num_parents);
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gate->reg = reg;
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gate->bit_idx = SUN8I_MBUS_ENABLE;
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gate->lock = &sun8i_a23_mbus_lock;
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div->reg = reg;
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div->shift = SUN8I_MBUS_DIV_SHIFT;
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div->width = SUN8I_MBUS_DIV_WIDTH;
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div->lock = &sun8i_a23_mbus_lock;
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mux->reg = reg;
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mux->shift = SUN8I_MBUS_MUX_SHIFT;
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mux->mask = SUN8I_MBUS_MUX_MASK;
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mux->lock = &sun8i_a23_mbus_lock;
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clk = clk_register_composite(NULL, clk_name, parents, num_parents,
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&mux->hw, &clk_mux_ops,
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&div->hw, &clk_divider_ops,
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&gate->hw, &clk_gate_ops,
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0);
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if (IS_ERR(clk))
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goto err_free_gate;
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err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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if (err)
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goto err_unregister_clk;
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/* The MBUS clocks needs to be always enabled */
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__clk_get(mbus);
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clk_prepare_enable(mbus);
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__clk_get(clk);
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clk_prepare_enable(clk);
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return;
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err_unregister_clk:
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/* TODO: The composite clock stuff will leak a bit here. */
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clk_unregister(clk);
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err_free_gate:
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kfree(gate);
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err_free_mux:
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kfree(mux);
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err_free_div:
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kfree(div);
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err_unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);
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