qla2xxx: Fix sparse annotations
This patch removes 21 casts between an __iomem pointer type and another data type but also introduces five new casts (see also the casts with "__force"). Although this patch does not change any functionality, IMHO the code with __force casts needs further review. Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com> Acked-by: Himanshu Madhani <himanshu.madhani@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Odin.com>
This commit is contained in:
Bart Van Assche
James Bottomley
parent
118e2ef9df
commit
8dfa4b5a9b
6 changed files with 71 additions and 82 deletions
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@ -3418,9 +3418,9 @@ struct qla_hw_data {
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mempool_t *ctx_mempool;
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#define FCP_CMND_DMA_POOL_SIZE 512
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unsigned long nx_pcibase; /* Base I/O address */
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uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
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unsigned long nxdb_wr_ptr; /* Door bell write pointer */
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void __iomem *nx_pcibase; /* Base I/O address */
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void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
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void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
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uint32_t crb_win;
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uint32_t curr_window;
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@ -2507,16 +2507,12 @@ qla82xx_start_scsi(srb_t *sp)
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/* write, read and verify logic */
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dbval = dbval | (req->id << 8) | (req->ring_index << 16);
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if (ql2xdbwr)
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qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
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qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, dbval);
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else {
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WRT_REG_DWORD(
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(unsigned long __iomem *)ha->nxdb_wr_ptr,
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dbval);
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WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
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wmb();
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while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
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WRT_REG_DWORD(
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(unsigned long __iomem *)ha->nxdb_wr_ptr,
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dbval);
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while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
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WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
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wmb();
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}
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}
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@ -1239,7 +1239,7 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
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"Entered %s.\n", __func__);
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if (IS_P3P_TYPE(ha) && ql2xdbwr)
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qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
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qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
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(0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
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if (ha->flags.npiv_supported)
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@ -862,7 +862,7 @@ qlafx00_config_queues(struct scsi_qla_host *vha)
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dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
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req->length = ha->req_que_len;
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req->ring = (void *)ha->iobase + ha->req_que_off;
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req->ring = (void __force *)ha->iobase + ha->req_que_off;
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req->dma = bar2_hdl + ha->req_que_off;
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if ((!req->ring) || (req->length == 0)) {
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ql_log_pci(ql_log_info, ha->pdev, 0x012f,
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@ -877,7 +877,7 @@ qlafx00_config_queues(struct scsi_qla_host *vha)
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ha->req_que_off, (u64)req->dma);
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rsp->length = ha->rsp_que_len;
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rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
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rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
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rsp->dma = bar2_hdl + ha->rsp_que_off;
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if ((!rsp->ring) || (rsp->length == 0)) {
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ql_log_pci(ql_log_info, ha->pdev, 0x0131,
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@ -1425,7 +1425,7 @@ qlafx00_init_response_q_entries(struct rsp_que *rsp)
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pkt = rsp->ring_ptr;
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for (cnt = 0; cnt < rsp->length; cnt++) {
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pkt->signature = RESPONSE_PROCESSED;
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WRT_REG_DWORD((void __iomem *)&pkt->signature,
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WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
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RESPONSE_PROCESSED);
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pkt++;
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}
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@ -347,32 +347,31 @@ char *qdev_state(uint32_t dev_state)
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}
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/*
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* In: 'off' is offset from CRB space in 128M pci map
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* Out: 'off' is 2M pci map addr
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* In: 'off_in' is offset from CRB space in 128M pci map
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* Out: 'off_out' is 2M pci map addr
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* side effect: lock crb window
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*/
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static void
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qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
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qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
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void __iomem **off_out)
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{
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u32 win_read;
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scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
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ha->crb_win = CRB_HI(*off);
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writel(ha->crb_win,
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(void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
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ha->crb_win = CRB_HI(off_in);
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writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
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/* Read back value to make sure write has gone through before trying
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* to use it.
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*/
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win_read = RD_REG_DWORD((void __iomem *)
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(CRB_WINDOW_2M + ha->nx_pcibase));
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win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
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if (win_read != ha->crb_win) {
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ql_dbg(ql_dbg_p3p, vha, 0xb000,
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"%s: Written crbwin (0x%x) "
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"!= Read crbwin (0x%x), off=0x%lx.\n",
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__func__, ha->crb_win, win_read, *off);
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__func__, ha->crb_win, win_read, off_in);
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}
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*off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
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*off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
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}
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static inline unsigned long
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@ -417,29 +416,30 @@ qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
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}
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static int
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qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
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qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
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void __iomem **off_out)
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{
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struct crb_128M_2M_sub_block_map *m;
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if (*off >= QLA82XX_CRB_MAX)
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if (off_in >= QLA82XX_CRB_MAX)
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return -1;
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if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
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*off = (*off - QLA82XX_PCI_CAMQM) +
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if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
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*off_out = (off_in - QLA82XX_PCI_CAMQM) +
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QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
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return 0;
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}
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if (*off < QLA82XX_PCI_CRBSPACE)
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if (off_in < QLA82XX_PCI_CRBSPACE)
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return -1;
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*off -= QLA82XX_PCI_CRBSPACE;
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*off_out = (void __iomem *)(off_in - QLA82XX_PCI_CRBSPACE);
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/* Try direct map */
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m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
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m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
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if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
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*off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
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if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
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*off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
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return 0;
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}
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/* Not in direct map, use crb window */
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@ -465,19 +465,20 @@ static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
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}
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int
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qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
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qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
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{
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void __iomem *off;
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unsigned long flags = 0;
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int rv;
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rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
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rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
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BUG_ON(rv == -1);
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if (rv == 1) {
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write_lock_irqsave(&ha->hw_lock, flags);
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qla82xx_crb_win_lock(ha);
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qla82xx_pci_set_crbwindow_2M(ha, &off);
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qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
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}
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writel(data, (void __iomem *)off);
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@ -490,22 +491,23 @@ qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
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}
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int
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qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
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qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
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{
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void __iomem *off;
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unsigned long flags = 0;
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int rv;
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u32 data;
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rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
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rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
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BUG_ON(rv == -1);
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if (rv == 1) {
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write_lock_irqsave(&ha->hw_lock, flags);
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qla82xx_crb_win_lock(ha);
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qla82xx_pci_set_crbwindow_2M(ha, &off);
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qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
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}
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data = RD_REG_DWORD((void __iomem *)off);
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data = RD_REG_DWORD(off);
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if (rv == 1) {
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qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
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@ -919,20 +921,18 @@ qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
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{
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uint32_t off_value, rval = 0;
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WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
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(off & 0xFFFF0000));
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WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
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/* Read back value to make sure write has gone through */
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RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
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RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
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off_value = (off & 0x0000FFFF);
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if (flag)
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WRT_REG_DWORD((void __iomem *)
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(off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
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data);
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WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
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data);
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else
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rval = RD_REG_DWORD((void __iomem *)
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(off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
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rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
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ha->nx_pcibase);
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return rval;
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}
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@ -1660,8 +1660,7 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
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}
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len = pci_resource_len(ha->pdev, 0);
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ha->nx_pcibase =
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(unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
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ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
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if (!ha->nx_pcibase) {
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ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
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"Cannot remap pcibase MMIO, aborting.\n");
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@ -1670,17 +1669,13 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
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/* Mapping of IO base pointer */
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if (IS_QLA8044(ha)) {
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ha->iobase =
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(device_reg_t *)((uint8_t *)ha->nx_pcibase);
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ha->iobase = ha->nx_pcibase;
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} else if (IS_QLA82XX(ha)) {
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ha->iobase =
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(device_reg_t *)((uint8_t *)ha->nx_pcibase +
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0xbc000 + (ha->pdev->devfn << 11));
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ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
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}
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if (!ql2xdbwr) {
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ha->nxdb_wr_ptr =
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(unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
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ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
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(ha->pdev->devfn << 12)), 4);
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if (!ha->nxdb_wr_ptr) {
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ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
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@ -1691,10 +1686,10 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
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/* Mapping of IO base pointer,
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* door bell read and write pointer
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*/
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ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
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ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
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(ha->pdev->devfn * 8);
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} else {
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ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
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ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
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QLA82XX_CAMRAM_DB1 :
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QLA82XX_CAMRAM_DB2);
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}
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@ -1704,12 +1699,12 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
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ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
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"nx_pci_base=%p iobase=%p "
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"max_req_queues=%d msix_count=%d.\n",
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(void *)ha->nx_pcibase, ha->iobase,
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ha->nx_pcibase, ha->iobase,
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ha->max_req_queues, ha->msix_count);
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
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"nx_pci_base=%p iobase=%p "
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"max_req_queues=%d msix_count=%d.\n",
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(void *)ha->nx_pcibase, ha->iobase,
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ha->nx_pcibase, ha->iobase,
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ha->max_req_queues, ha->msix_count);
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return 0;
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@ -1774,9 +1769,9 @@ void qla82xx_config_rings(struct scsi_qla_host *vha)
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icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
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icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
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WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0);
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WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0);
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WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0);
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WRT_REG_DWORD(®->req_q_out[0], 0);
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WRT_REG_DWORD(®->rsp_q_in[0], 0);
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WRT_REG_DWORD(®->rsp_q_out[0], 0);
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}
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static int
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@ -2799,13 +2794,12 @@ qla82xx_start_iocbs(scsi_qla_host_t *vha)
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dbval = dbval | (req->id << 8) | (req->ring_index << 16);
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if (ql2xdbwr)
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qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
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qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
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else {
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WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
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WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
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wmb();
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while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
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WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
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dbval);
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while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
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WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
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wmb();
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}
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}
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@ -3836,8 +3830,7 @@ qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
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loop_cnt = ocm_hdr->op_count;
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for (i = 0; i < loop_cnt; i++) {
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r_value = RD_REG_DWORD((void __iomem *)
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(r_addr + ha->nx_pcibase));
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r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
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*data_ptr++ = cpu_to_le32(r_value);
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r_addr += r_stride;
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}
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@ -137,39 +137,39 @@ qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
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}
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static inline void
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qla27xx_read8(void *window, void *buf, ulong *len)
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qla27xx_read8(void __iomem *window, void *buf, ulong *len)
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{
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uint8_t value = ~0;
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if (buf) {
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value = RD_REG_BYTE((__iomem void *)window);
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value = RD_REG_BYTE(window);
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}
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qla27xx_insert32(value, buf, len);
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}
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static inline void
|
||||
qla27xx_read16(void *window, void *buf, ulong *len)
|
||||
qla27xx_read16(void __iomem *window, void *buf, ulong *len)
|
||||
{
|
||||
uint16_t value = ~0;
|
||||
|
||||
if (buf) {
|
||||
value = RD_REG_WORD((__iomem void *)window);
|
||||
value = RD_REG_WORD(window);
|
||||
}
|
||||
qla27xx_insert32(value, buf, len);
|
||||
}
|
||||
|
||||
static inline void
|
||||
qla27xx_read32(void *window, void *buf, ulong *len)
|
||||
qla27xx_read32(void __iomem *window, void *buf, ulong *len)
|
||||
{
|
||||
uint32_t value = ~0;
|
||||
|
||||
if (buf) {
|
||||
value = RD_REG_DWORD((__iomem void *)window);
|
||||
value = RD_REG_DWORD(window);
|
||||
}
|
||||
qla27xx_insert32(value, buf, len);
|
||||
}
|
||||
|
||||
static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
|
||||
static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *)
|
||||
{
|
||||
return
|
||||
(width == 1) ? qla27xx_read8 :
|
||||
|
|
@ -181,7 +181,7 @@ static inline void
|
|||
qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
|
||||
uint offset, void *buf, ulong *len)
|
||||
{
|
||||
void *window = (void *)reg + offset;
|
||||
void __iomem *window = (void __iomem *)reg + offset;
|
||||
|
||||
qla27xx_read32(window, buf, len);
|
||||
}
|
||||
|
|
@ -202,8 +202,8 @@ qla27xx_read_window(__iomem struct device_reg_24xx *reg,
|
|||
uint32_t addr, uint offset, uint count, uint width, void *buf,
|
||||
ulong *len)
|
||||
{
|
||||
void *window = (void *)reg + offset;
|
||||
void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
|
||||
void __iomem *window = (void __iomem *)reg + offset;
|
||||
void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
|
||||
|
||||
qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
|
||||
while (count--) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue