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MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts

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EMMA's GPIO interrupts are latched by GPIO interrupt status register.
In this case, we're encouraged to use handle_edge_irq() handler.

The following changes are made along with replacing set_irq_chip() with
set_irq_chip_and_handler_name(,,handle_edge_irq,"edge"):

* Fix emma2rh_gpio_irq_ack not to disable interrupts

  With handle_edge_irq(), we're not expected to disable interrupts
  when chip->ack is served, so fix it accordingly.  We also add a new
  emma2rh_gpio_irq_mask_ack() for chip->mask_ack operation, instead.

* Remove emma2rh_gpio_irq_end(), as chip->end is no longer served.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Shinya Kuribayashi 2009-03-21 22:06:14 +09:00 committed by Ralf Baechle
parent fb2826b7f6
commit 8da55bb258
1 changed files with 10 additions and 18 deletions
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28
arch/mips/emma/markeins/irq.c
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@ -148,6 +148,12 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
} }
static void emma2rh_gpio_irq_ack(unsigned int irq) static void emma2rh_gpio_irq_ack(unsigned int irq)
{
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
}
static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
{ {
u32 reg; u32 reg;
@ -159,27 +165,12 @@ static void emma2rh_gpio_irq_ack(unsigned int irq)
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
} }
static void emma2rh_gpio_irq_end(unsigned int irq)
{
u32 reg;
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
irq -= EMMA2RH_GPIO_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
}
struct irq_chip emma2rh_gpio_irq_controller = { struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq", .name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack, .ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable, .mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack, .mask_ack = emma2rh_gpio_irq_mask_ack,
.unmask = emma2rh_gpio_irq_enable, .unmask = emma2rh_gpio_irq_enable,
.end = emma2rh_gpio_irq_end,
}; };
void emma2rh_gpio_irq_init(void) void emma2rh_gpio_irq_init(void)
@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void)
u32 i; u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller); &emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
} }
static struct irqaction irq_cascade = { static struct irqaction irq_cascade = {