arm/imx: remove imx_idle hook and use pm_idle instead
The patch removes imx_idle hook and use pm_idle instead to get imx arch_idle prepared for the cleanup. It's suggested by Russel King as below. > The final removal of mach/system.h depends on getting rid of the arch_idle > thing. While going through these headers, I was dismayed to find these: > > arch/arm/mach-s3c2410/include/mach/system.h:void (*s3c24xx_idle)(void); > arch/arm/plat-mxc/include/mach/system.h:extern void (*imx_idle)(void); > > when we have a perfectly good pm_idle hook already in place - so there's > no excuse for these especially when other platforms are already using > pm_idle to hook their platform specific idle function into. This is > something that better be gone at the next merge window! Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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5 changed files with 33 additions and 35 deletions
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@ -33,29 +33,32 @@
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static void imx3_idle(void)
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{
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unsigned long reg = 0;
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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if (!need_resched())
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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local_irq_enable();
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}
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static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
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@ -143,7 +146,7 @@ void __init imx31_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX31);
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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imx_idle = imx3_idle;
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pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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}
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@ -152,7 +155,7 @@ void __init imx35_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX35);
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mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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imx_idle = imx3_idle;
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pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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}
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@ -23,7 +23,9 @@
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static void imx5_idle(void)
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{
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (!need_resched())
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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local_irq_enable();
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}
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/*
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@ -89,7 +91,7 @@ void __init imx51_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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imx_idle = imx5_idle;
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pm_idle = imx5_idle;
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}
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void __init imx53_init_early(void)
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@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode {
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};
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extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
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extern void (*imx_idle)(void);
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extern void imx_print_silicon_rev(const char *cpu, int srev);
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void avic_handle_irq(struct pt_regs *);
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@ -17,14 +17,9 @@
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#ifndef __ASM_ARCH_MXC_SYSTEM_H__
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#define __ASM_ARCH_MXC_SYSTEM_H__
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extern void (*imx_idle)(void);
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static inline void arch_idle(void)
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{
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if (imx_idle != NULL)
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(imx_idle)();
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else
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cpu_do_idle();
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cpu_do_idle();
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}
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void arch_reset(char mode, const char *cmd);
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@ -28,7 +28,6 @@
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#include <asm/system.h>
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#include <asm/mach-types.h>
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void (*imx_idle)(void) = NULL;
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void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
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static void __iomem *wdog_base;
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