soc: qcom: Introduce pon ops for sdx55
Introduce new pon ops for sdx55 to be used in Kona with external modem. Change-Id: I039594eb30cb4ec9f43819a5f7d4c1048477e4bd Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
This commit is contained in:
Rishabh Bhatnagar
parent
93d797f613
commit
8c5156ceee
4 changed files with 173 additions and 1 deletions
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@ -1045,6 +1045,120 @@ static int sdx50m_setup_hw(struct mdm_ctrl *mdm,
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return ret;
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}
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static int sdx55m_setup_hw(struct mdm_ctrl *mdm,
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const struct mdm_ops *ops,
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struct platform_device *pdev)
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{
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int ret;
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struct device_node *node;
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struct esoc_clink *esoc;
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const struct esoc_clink_ops *const clink_ops = ops->clink_ops;
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const struct mdm_pon_ops *pon_ops = ops->pon_ops;
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mdm->dev = &pdev->dev;
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mdm->pon_ops = pon_ops;
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node = pdev->dev.of_node;
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esoc = devm_kzalloc(mdm->dev, sizeof(*esoc), GFP_KERNEL);
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if (IS_ERR_OR_NULL(esoc)) {
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dev_err(mdm->dev, "cannot allocate esoc device\n");
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return PTR_ERR(esoc);
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}
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esoc->pdev = pdev;
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mdm->mdm_queue = alloc_workqueue("mdm_queue", 0, 0);
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if (!mdm->mdm_queue) {
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dev_err(mdm->dev, "could not create mdm_queue\n");
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return -ENOMEM;
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}
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mdm->irq_mask = 0;
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mdm->ready = false;
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ret = mdm_dt_parse_gpios(mdm);
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if (ret) {
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esoc_mdm_log("Failed to parse DT gpios\n");
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dev_err(mdm->dev, "Failed to parse DT gpios\n");
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goto err_destroy_wrkq;
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}
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ret = mdm_pon_dt_init(mdm);
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if (ret) {
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esoc_mdm_log("Failed to parse PON DT gpios\n");
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dev_err(mdm->dev, "Failed to parse PON DT gpio\n");
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goto err_destroy_wrkq;
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}
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ret = mdm_pinctrl_init(mdm);
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if (ret) {
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esoc_mdm_log("Failed to init pinctrl\n");
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dev_err(mdm->dev, "Failed to init pinctrl\n");
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goto err_destroy_wrkq;
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}
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ret = mdm_pon_setup(mdm);
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if (ret) {
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esoc_mdm_log("Failed to setup PON\n");
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dev_err(mdm->dev, "Failed to setup PON\n");
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goto err_destroy_wrkq;
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}
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ret = mdm_configure_ipc(mdm, pdev);
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if (ret) {
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esoc_mdm_log("Failed to configure the ipc\n");
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dev_err(mdm->dev, "Failed to configure the ipc\n");
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goto err_release_ipc;
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}
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esoc->name = SDX55M_LABEL;
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mdm->dual_interface = of_property_read_bool(node,
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"qcom,mdm-dual-link");
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esoc->link_name = SDX55M_PCIE;
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ret = of_property_read_string(node, "qcom,mdm-link-info",
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&esoc->link_info);
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if (ret)
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dev_info(mdm->dev, "esoc link info missing\n");
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mdm->skip_restart_for_mdm_crash = of_property_read_bool(node,
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"qcom,esoc-skip-restart-for-mdm-crash");
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esoc->clink_ops = clink_ops;
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esoc->parent = mdm->dev;
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esoc->owner = THIS_MODULE;
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esoc->np = pdev->dev.of_node;
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set_esoc_clink_data(esoc, mdm);
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ret = esoc_clink_register(esoc);
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if (ret) {
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esoc_mdm_log("esoc registration failed\n");
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dev_err(mdm->dev, "esoc registration failed\n");
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goto err_free_irq;
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}
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dev_dbg(mdm->dev, "esoc registration done\n");
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esoc_mdm_log("Done configuring the GPIOs and esoc registration\n");
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init_completion(&mdm->debug_done);
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INIT_WORK(&mdm->mdm_status_work, mdm_status_fn);
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INIT_WORK(&mdm->restart_reason_work, mdm_get_restart_reason);
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INIT_DELAYED_WORK(&mdm->mdm2ap_status_check_work, mdm2ap_status_check);
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mdm->get_restart_reason = false;
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mdm->debug_fail = false;
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mdm->esoc = esoc;
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mdm->init = 0;
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mdm_debug_gpio_ipc_log(mdm);
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return 0;
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err_free_irq:
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mdm_free_irq(mdm);
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err_release_ipc:
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mdm_release_ipc_gpio(mdm);
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err_destroy_wrkq:
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destroy_workqueue(mdm->mdm_queue);
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return ret;
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}
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static struct esoc_clink_ops mdm_cops = {
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.cmd_exe = mdm_cmd_exe,
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.get_status = mdm_get_status,
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@ -1064,11 +1178,19 @@ static struct mdm_ops sdx50m_ops = {
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.pon_ops = &sdx50m_pon_ops,
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};
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static struct mdm_ops sdx55m_ops = {
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.clink_ops = &mdm_cops,
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.config_hw = sdx55m_setup_hw,
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.pon_ops = &sdx55m_pon_ops,
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};
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static const struct of_device_id mdm_dt_match[] = {
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{ .compatible = "qcom,ext-mdm9x55",
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.data = &mdm9x55_ops, },
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{ .compatible = "qcom,ext-sdx50m",
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.data = &sdx50m_ops, },
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{ .compatible = "qcom,ext-sdx55m",
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.data = &sdx55m_ops, },
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{},
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};
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MODULE_DEVICE_TABLE(of, mdm_dt_match);
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@ -507,6 +507,10 @@ static struct esoc_compat compat_table[] = {
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.name = "SDX50M",
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.data = NULL,
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},
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{
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.name = "SDX55M",
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.data = NULL,
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},
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};
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static struct esoc_drv esoc_ssr_drv = {
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@ -55,7 +55,43 @@ static int sdx50m_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic)
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* Allow PS hold assert to be detected
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*/
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if (!atomic)
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usleep_range(80000,180000);
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usleep_range(80000, 180000);
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else
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/*
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* The flow falls through this path as a part of the
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* panic handler, which has to executed atomically.
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*/
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mdelay(100);
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esoc_mdm_log("Setting AP2MDM_SOFT_RESET = %d\n",
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soft_reset_direction_de_assert);
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gpio_direction_output(MDM_GPIO(mdm, AP2MDM_SOFT_RESET),
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soft_reset_direction_de_assert);
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return 0;
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}
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/* This function can be called from atomic context. */
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static int sdx55m_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic)
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{
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int soft_reset_direction_assert = 0,
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soft_reset_direction_de_assert = 1;
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if (mdm->soft_reset_inverted) {
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soft_reset_direction_assert = 1;
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soft_reset_direction_de_assert = 0;
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}
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esoc_mdm_log("RESET GPIO value (before doing a reset): %d\n",
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gpio_get_value(MDM_GPIO(mdm, AP2MDM_SOFT_RESET)));
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esoc_mdm_log("Setting AP2MDM_SOFT_RESET = %d\n",
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soft_reset_direction_assert);
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gpio_direction_output(MDM_GPIO(mdm, AP2MDM_SOFT_RESET),
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soft_reset_direction_assert);
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/*
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* Allow PS hold assert to be detected
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*/
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if (!atomic)
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usleep_range(80000, 180000);
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else
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/*
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* The flow falls through this path as a part of the
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@ -263,3 +299,10 @@ struct mdm_pon_ops sdx50m_pon_ops = {
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.dt_init = mdm4x_pon_dt_init,
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.setup = mdm4x_pon_setup,
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};
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struct mdm_pon_ops sdx55m_pon_ops = {
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.pon = mdm4x_do_first_power_on,
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.soft_reset = sdx55m_toggle_soft_reset,
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.dt_init = mdm4x_pon_dt_init,
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.setup = mdm4x_pon_setup,
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};
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@ -24,6 +24,8 @@
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#define MDM9x55_PCIE "PCIe"
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#define SDX50M_LABEL "SDX50M"
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#define SDX50M_PCIE "PCIe"
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#define SDX55M_LABEL "SDX55M"
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#define SDX55M_PCIE "PCIe"
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#define MDM2AP_STATUS_TIMEOUT_MS 120000L
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#define MDM_MODEM_TIMEOUT 3000
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#define DEF_RAMDUMP_TIMEOUT 120000
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@ -145,4 +147,5 @@ static inline int mdm_pon_setup(struct mdm_ctrl *mdm)
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extern struct mdm_pon_ops mdm9x55_pon_ops;
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extern struct mdm_pon_ops sdx50m_pon_ops;
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extern struct mdm_pon_ops sdx55m_pon_ops;
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#endif
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