[POWERPC] maple/pci iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
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62034f0338
commit
8c42ec2c99
1 changed files with 30 additions and 30 deletions
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@ -96,14 +96,14 @@ static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
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1UL;
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1UL;
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}
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}
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static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
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static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
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u8 bus, u8 dev_fn, u8 offset)
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u8 bus, u8 dev_fn, u8 offset)
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{
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{
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unsigned int caddr;
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unsigned int caddr;
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if (bus == hose->first_busno) {
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if (bus == hose->first_busno) {
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if (dev_fn < (11 << 3))
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if (dev_fn < (11 << 3))
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return 0;
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return NULL;
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caddr = u3_agp_cfa0(dev_fn, offset);
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caddr = u3_agp_cfa0(dev_fn, offset);
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} else
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} else
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caddr = u3_agp_cfa1(bus, dev_fn, offset);
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caddr = u3_agp_cfa1(bus, dev_fn, offset);
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@ -114,14 +114,14 @@ static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
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} while (in_le32(hose->cfg_addr) != caddr);
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} while (in_le32(hose->cfg_addr) != caddr);
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offset &= 0x07;
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offset &= 0x07;
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return ((unsigned long)hose->cfg_data) + offset;
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return hose->cfg_data + offset;
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}
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}
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static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
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static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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int offset, int len, u32 *val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -136,13 +136,13 @@ static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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*val = in_8((u8 *)addr);
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*val = in_8(addr);
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break;
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break;
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case 2:
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case 2:
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*val = in_le16((u16 *)addr);
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*val = in_le16(addr);
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break;
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break;
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default:
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default:
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*val = in_le32((u32 *)addr);
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*val = in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -152,7 +152,7 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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int offset, int len, u32 val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -167,16 +167,16 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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out_8((u8 *)addr, val);
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out_8(addr, val);
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(void) in_8((u8 *)addr);
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(void) in_8(addr);
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break;
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break;
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case 2:
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case 2:
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out_le16((u16 *)addr, val);
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out_le16(addr, val);
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(void) in_le16((u16 *)addr);
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(void) in_le16(addr);
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break;
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break;
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default:
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default:
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out_le32((u32 *)addr, val);
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out_le32(addr, val);
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(void) in_le32((u32 *)addr);
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(void) in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -198,22 +198,22 @@ static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
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return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
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return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
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}
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}
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static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
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static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
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u8 bus, u8 devfn, u8 offset)
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u8 bus, u8 devfn, u8 offset)
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{
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{
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if (bus == hose->first_busno) {
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if (bus == hose->first_busno) {
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if (PCI_SLOT(devfn) == 0)
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if (PCI_SLOT(devfn) == 0)
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return 0;
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return NULL;
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return ((unsigned long)hose->cfg_data) + u3_ht_cfa0(devfn, offset);
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return hose->cfg_data + u3_ht_cfa0(devfn, offset);
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} else
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} else
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return ((unsigned long)hose->cfg_data) + u3_ht_cfa1(bus, devfn, offset);
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return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
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}
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}
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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int offset, int len, u32 *val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -232,13 +232,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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*val = in_8((u8 *)addr);
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*val = in_8(addr);
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break;
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break;
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case 2:
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case 2:
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*val = in_le16((u16 *)addr);
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*val = in_le16(addr);
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break;
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break;
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default:
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default:
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*val = in_le32((u32 *)addr);
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*val = in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -248,7 +248,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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int offset, int len, u32 val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -266,16 +266,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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out_8((u8 *)addr, val);
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out_8(addr, val);
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(void) in_8((u8 *)addr);
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(void) in_8(addr);
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break;
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break;
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case 2:
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case 2:
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out_le16((u16 *)addr, val);
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out_le16(addr, val);
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(void) in_le16((u16 *)addr);
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(void) in_le16(addr);
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break;
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break;
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default:
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default:
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out_le32((u32 *)addr, val);
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out_le32(addr, val);
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(void) in_le32((u32 *)addr);
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(void) in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -315,7 +315,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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* the reg address cell, we shall fix that by killing struct
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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* reg_property and using some accessor functions instead
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*/
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*/
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hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
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hose->cfg_data = ioremap(0xf2000000, 0x02000000);
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hose->first_busno = 0;
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hose->first_busno = 0;
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hose->last_busno = 0xef;
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hose->last_busno = 0xef;
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