sh: dmaengine support for SH7757
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
53bc18ef4d
commit
8ac53ed537
3 changed files with 554 additions and 1 deletions
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@ -40,6 +40,11 @@
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0x00100000
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#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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@ -251,4 +251,36 @@ enum {
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GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
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};
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enum {
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SHDMA_SLAVE_SDHI_TX,
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SHDMA_SLAVE_SDHI_RX,
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SHDMA_SLAVE_MMCIF_TX,
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SHDMA_SLAVE_MMCIF_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_RIIC0_TX,
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SHDMA_SLAVE_RIIC0_RX,
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SHDMA_SLAVE_RIIC1_TX,
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SHDMA_SLAVE_RIIC1_RX,
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SHDMA_SLAVE_RIIC2_TX,
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SHDMA_SLAVE_RIIC2_RX,
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SHDMA_SLAVE_RIIC3_TX,
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SHDMA_SLAVE_RIIC3_RX,
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SHDMA_SLAVE_RIIC4_TX,
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SHDMA_SLAVE_RIIC4_RX,
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SHDMA_SLAVE_RIIC5_TX,
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SHDMA_SLAVE_RIIC5_RX,
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SHDMA_SLAVE_RIIC6_TX,
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SHDMA_SLAVE_RIIC6_RX,
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SHDMA_SLAVE_RIIC7_TX,
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SHDMA_SLAVE_RIIC7_RX,
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SHDMA_SLAVE_RIIC8_TX,
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SHDMA_SLAVE_RIIC8_RX,
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SHDMA_SLAVE_RIIC9_TX,
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SHDMA_SLAVE_RIIC9_RX,
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};
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#endif /* __ASM_SH7757_H__ */
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@ -1,7 +1,7 @@
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/*
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* SH7757 Setup
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Copyright (C) 2009, 2011 Renesas Solutions Corp.
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*
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* based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
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*
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@ -16,6 +16,10 @@
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/sh_timer.h>
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#include <linux/sh_dma.h>
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#include <cpu/dma-register.h>
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#include <cpu/sh7757.h>
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xfe4b0000, /* SCIF2 */
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@ -136,6 +140,514 @@ static struct resource spi0_resources[] = {
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},
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};
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/* DMA */
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static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SDHI_TX,
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.addr = 0x1fe50030,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xc5,
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},
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{
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.slave_id = SHDMA_SLAVE_SDHI_RX,
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.addr = 0x1fe50030,
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.chcr = DM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xc6,
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},
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{
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.slave_id = SHDMA_SLAVE_MMCIF_TX,
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.addr = 0x1fcb0034,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xd3,
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},
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{
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.slave_id = SHDMA_SLAVE_MMCIF_RX,
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.addr = 0x1fcb0034,
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.chcr = DM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xd7,
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},
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};
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static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SCIF2_TX,
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.addr = 0x1f4b000c,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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},
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{
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.slave_id = SHDMA_SLAVE_SCIF2_RX,
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.addr = 0x1f4b0014,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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},
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{
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.slave_id = SHDMA_SLAVE_SCIF3_TX,
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.addr = 0x1f4c000c,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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},
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{
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.slave_id = SHDMA_SLAVE_SCIF3_RX,
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.addr = 0x1f4c0014,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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},
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{
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.slave_id = SHDMA_SLAVE_SCIF4_TX,
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.addr = 0x1f4d000c,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x41,
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},
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{
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.slave_id = SHDMA_SLAVE_SCIF4_RX,
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.addr = 0x1f4d0014,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x42,
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},
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};
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static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_RIIC0_TX,
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.addr = 0x1e500012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC0_RX,
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.addr = 0x1e500013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC1_TX,
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.addr = 0x1e510012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC1_RX,
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.addr = 0x1e510013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC2_TX,
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.addr = 0x1e520012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xa1,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC2_RX,
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.addr = 0x1e520013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xa2,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC3_TX,
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.addr = 0x1e530012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xab,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC3_RX,
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.addr = 0x1e530013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xaf,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC4_TX,
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.addr = 0x1e540012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xc1,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC4_RX,
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.addr = 0x1e540013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0xc2,
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},
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};
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static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_RIIC5_TX,
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.addr = 0x1e550012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC5_RX,
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.addr = 0x1e550013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC6_TX,
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.addr = 0x1e560012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC6_RX,
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.addr = 0x1e560013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC7_TX,
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.addr = 0x1e570012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x41,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC7_RX,
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.addr = 0x1e570013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x42,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC8_TX,
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.addr = 0x1e580012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x45,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC8_RX,
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.addr = 0x1e580013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x46,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC9_TX,
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.addr = 0x1e590012,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x51,
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},
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{
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.slave_id = SHDMA_SLAVE_RIIC9_RX,
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.addr = 0x1e590013,
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.chcr = SM_INC | 0x800 | 0x40000000 |
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TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x52,
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},
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};
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static const struct sh_dmae_channel sh7757_dmae_channels[] = {
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{
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.offset = 0,
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.dmars = 0,
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.dmars_bit = 0,
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}, {
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.offset = 0x10,
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.dmars = 0,
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.dmars_bit = 8,
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}, {
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.offset = 0x20,
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.dmars = 4,
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.dmars_bit = 0,
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}, {
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.offset = 0x30,
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.dmars = 4,
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.dmars_bit = 8,
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}, {
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.offset = 0x50,
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.dmars = 8,
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.dmars_bit = 0,
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}, {
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.offset = 0x60,
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.dmars = 8,
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.dmars_bit = 8,
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}
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};
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static const unsigned int ts_shift[] = TS_SHIFT;
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static struct sh_dmae_pdata dma0_platform_data = {
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.slave = sh7757_dmae0_slaves,
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.slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
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.channel = sh7757_dmae_channels,
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.channel_num = ARRAY_SIZE(sh7757_dmae_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct sh_dmae_pdata dma1_platform_data = {
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.slave = sh7757_dmae1_slaves,
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.slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
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.channel = sh7757_dmae_channels,
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.channel_num = ARRAY_SIZE(sh7757_dmae_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct sh_dmae_pdata dma2_platform_data = {
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.slave = sh7757_dmae2_slaves,
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.slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
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.channel = sh7757_dmae_channels,
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.channel_num = ARRAY_SIZE(sh7757_dmae_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct sh_dmae_pdata dma3_platform_data = {
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.slave = sh7757_dmae3_slaves,
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.slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
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.channel = sh7757_dmae_channels,
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.channel_num = ARRAY_SIZE(sh7757_dmae_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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/* channel 0 to 5 */
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static struct resource sh7757_dmae0_resources[] = {
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[0] = {
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/* Channel registers and DMAOR */
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.start = 0xff608020,
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.end = 0xff60808f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* DMARSx */
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.start = 0xff609000,
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.end = 0xff60900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 34,
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.end = 34,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
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},
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};
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/* channel 6 to 11 */
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static struct resource sh7757_dmae1_resources[] = {
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[0] = {
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/* Channel registers and DMAOR */
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.start = 0xff618020,
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.end = 0xff61808f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* DMARSx */
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.start = 0xff619000,
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.end = 0xff61900b,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMA error */
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.start = 34,
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.end = 34,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
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},
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{
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/* IRQ for channels 4 */
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.start = 46,
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.end = 46,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 5 */
|
||||
.start = 46,
|
||||
.end = 46,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 6 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 7 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 8 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 9 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 10 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 11 */
|
||||
.start = 88,
|
||||
.end = 88,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
};
|
||||
|
||||
/* channel 12 to 17 */
|
||||
static struct resource sh7757_dmae2_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xff708020,
|
||||
.end = 0xff70808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
/* DMARSx */
|
||||
.start = 0xff709000,
|
||||
.end = 0xff70900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error */
|
||||
.start = 323,
|
||||
.end = 323,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 12 to 16 */
|
||||
.start = 272,
|
||||
.end = 276,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channel 17 */
|
||||
.start = 279,
|
||||
.end = 279,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
/* channel 18 to 23 */
|
||||
static struct resource sh7757_dmae3_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xff718020,
|
||||
.end = 0xff71808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
/* DMARSx */
|
||||
.start = 0xff719000,
|
||||
.end = 0xff71900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error */
|
||||
.start = 324,
|
||||
.end = 324,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 18 to 22 */
|
||||
.start = 280,
|
||||
.end = 284,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channel 23 */
|
||||
.start = 288,
|
||||
.end = 288,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma0_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 0,
|
||||
.resource = sh7757_dmae0_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma1_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 1,
|
||||
.resource = sh7757_dmae1_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma2_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 2,
|
||||
.resource = sh7757_dmae2_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma3_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 3,
|
||||
.resource = sh7757_dmae3_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device spi0_device = {
|
||||
.name = "sh_spi",
|
||||
.id = 0,
|
||||
|
@ -153,6 +665,10 @@ static struct platform_device *sh7757_devices[] __initdata = {
|
|||
&scif4_device,
|
||||
&tmu0_device,
|
||||
&tmu1_device,
|
||||
&dma0_device,
|
||||
&dma1_device,
|
||||
&dma2_device,
|
||||
&dma3_device,
|
||||
&spi0_device,
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue