[ARM] pxa: make OHCI register definitions available to both pxa27x and pxa3xx
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
eric miao
Russell King
parent
f92a629cf7
commit
88d456386c
1 changed files with 71 additions and 68 deletions
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@ -1969,74 +1969,6 @@
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#define KPAS_SO (0x1 << 31)
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#define KPASMKPx_SO (0x1 << 31)
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/*
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* UHC: USB Host Controller (OHCI-like) register definitions
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*/
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#define UHC_BASE_PHYS (0x4C000000)
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#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
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#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
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#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
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#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
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#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
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#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
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#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
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#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
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#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
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#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
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#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
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#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
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#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
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#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
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#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
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#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
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#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
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#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
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#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
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#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
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#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
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#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
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#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
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#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
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#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
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#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
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#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
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#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
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#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
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#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
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#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
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#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
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#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
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#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
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#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
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#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
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#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
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#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
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#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
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#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
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#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
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#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
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#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
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#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
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#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
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#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
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Interrupt Enable*/
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#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
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#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
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#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
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/* Camera Interface */
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#define CICR0 __REG(0x50000000)
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#define CICR1 __REG(0x50000004)
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@ -2184,6 +2116,77 @@
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#endif
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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/*
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* UHC: USB Host Controller (OHCI-like) register definitions
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*/
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#define UHC_BASE_PHYS (0x4C000000)
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#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
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#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
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#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
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#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
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#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
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#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
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#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
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#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
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#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
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#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
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#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
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#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
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#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
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#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
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#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
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#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
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#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
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#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
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#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
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#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
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#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
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#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
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#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
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#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
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#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
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#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
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#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
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#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
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#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
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#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
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#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
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#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
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#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
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#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
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#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
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#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
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#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
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#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
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#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
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#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
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#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
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#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
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#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
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#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
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#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
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#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
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Interrupt Enable*/
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#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
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#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
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#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
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#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
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/* PWRMODE register M field values */
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#define PWRMODE_IDLE 0x1
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