Techwizz/kernel-fxtec-pro1x
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clk: Add additional checking to some clock driver functions

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Fix certain functions with potential for a NULL
pointer de-reference.

Change-Id: I855ef1d883a22616db7086bd5d47ee1f8e54694a
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2017-07-14 11:38:35 -07:00 committed by Gerrit - the friendly Code Review server
parent 8e3dc7f9cb
commit 88830b025b
3 changed files with 32 additions and 15 deletions
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3
drivers/clk/clk-divider.c
View file

@ -282,6 +282,9 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
unsigned long parent_rate, best = 0, now, maxdiv;
unsigned long parent_rate_saved = *best_parent_rate;
if (!hw || !parent)
return -EINVAL;
if (!rate)
rate = 1;

41
drivers/clk/qcom/clk-branch.c
View file

@ -248,13 +248,18 @@ static int clk_branch2_enable(struct clk_hw *hw)
static int clk_branch2_prepare(struct clk_hw *hw)
{
struct clk_branch *branch = to_clk_branch(hw);
struct clk_hw *parent = clk_hw_get_parent(hw);
unsigned long curr_rate, branch_rate = branch->rate;
struct clk_branch *branch;
struct clk_hw *parent;
unsigned long curr_rate;
int ret = 0;
if (!parent)
return -EPERM;
if (!hw)
return -EINVAL;
branch = to_clk_branch(hw);
parent = clk_hw_get_parent(hw);
if (!branch)
return -EINVAL;
/*
* Do the rate aggregation and scaling of the RCG in the prepare/
@ -262,12 +267,15 @@ static int clk_branch2_prepare(struct clk_hw *hw)
* votes on the voltage rails.
*/
if (branch->aggr_sibling_rates) {
if (!parent)
return -EINVAL;
curr_rate = clk_aggregate_rate(hw, parent->core);
if (branch_rate > curr_rate) {
ret = clk_set_rate(parent->clk, branch_rate);
if (branch->rate > curr_rate) {
ret = clk_set_rate(parent->clk, branch->rate);
if (ret) {
pr_err("Failed to scale %s to %lu\n",
clk_hw_get_name(parent), branch_rate);
clk_hw_get_name(parent), branch->rate);
goto exit;
}
}
@ -283,16 +291,23 @@ static void clk_branch2_disable(struct clk_hw *hw)
static void clk_branch2_unprepare(struct clk_hw *hw)
{
struct clk_branch *branch = to_clk_branch(hw);
struct clk_hw *parent = clk_hw_get_parent(hw);
unsigned long curr_rate, new_rate, branch_rate = branch->rate;
struct clk_branch *branch;
struct clk_hw *parent;
unsigned long curr_rate, new_rate;
if (!parent)
if (!hw)
return;
branch = to_clk_branch(hw);
parent = clk_hw_get_parent(hw);
if (!branch)
return;
if (branch->aggr_sibling_rates) {
if (!parent)
return;
new_rate = clk_aggregate_rate(hw, parent->core);
curr_rate = max(new_rate, branch_rate);
curr_rate = max(new_rate, branch->rate);
if (new_rate < curr_rate)
if (clk_set_rate(parent->clk, new_rate))
pr_err("Failed to scale %s to %lu\n",

3
drivers/clk/qcom/clk-rcg2.c
View file

@ -1004,15 +1004,14 @@ static int clk_dp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *parent = clk_hw_get_parent(hw);
struct freq_tbl f = { 0 };
unsigned long src_rate;
unsigned long num, den;
u32 mask = BIT(rcg->hid_width) - 1;
u32 hid_div, cfg;
int i, num_parents = clk_hw_get_num_parents(hw);
struct clk_hw *parent;
parent = clk_hw_get_parent(hw);
if (!parent)
return -EINVAL;