ARC: [intc] don't mask all IRQ by default
Hardware keeps them enabled on reset, and Linux needs to keep status quo. Any spurious interrupts will be reported/blocked by genirq. This helps remove a SMP IRQ quirk (next commit), where a peripheral IRQ is hard wired to core0, and request_irq()->unmask() happens on core1, keeping the IRQ masked on core0, needing an explicit unmask. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
parent
c16e3e2283
commit
878f46c71e
1 changed files with 1 additions and 6 deletions
|
@ -19,21 +19,16 @@
|
|||
|
||||
/*
|
||||
* Early Hardware specific Interrupt setup
|
||||
* -Platform independent, needed for each CPU (not foldable into init_IRQ)
|
||||
* -Called very early (start_kernel -> setup_arch -> setup_processor)
|
||||
* -Platform Independent (must for any ARC700)
|
||||
* -Needed for each CPU (hence not foldable into init_IRQ)
|
||||
*
|
||||
* what it does ?
|
||||
* -Disable all IRQs (on CPU side)
|
||||
* -Optionally, setup the High priority Interrupts as Level 2 IRQs
|
||||
*/
|
||||
void arc_init_IRQ(void)
|
||||
{
|
||||
int level_mask = 0;
|
||||
|
||||
/* Disable all IRQs: enable them as devices request */
|
||||
write_aux_reg(AUX_IENABLE, 0);
|
||||
|
||||
/* setup any high priority Interrupts (Level2 in ARCompact jargon) */
|
||||
level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
|
||||
level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
|
||||
|
|
Loading…
Reference in a new issue