Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Merge branch 'dt' of git://github.com/hzhuang1/linux into next/dt

Browse source 
* 'dt' of git://github.com/hzhuang1/linux:
  Documentation: update docs for mmp dt
  ARM: dts: refresh dts file for arch mmp
  ARM: mmp: support pxa910 with device tree
  ARM: mmp: support mmp2 with device tree
  gpio: pxa: parse gpio from DTS file
  ARM: mmp: support DT in timer
  ARM: mmp: support DT in irq
  ARM: mmp: append CONFIG_MACH_MMP2_DT
  ARM: mmp: fix build issue on mmp with device tree

Includes an update to v3-4-rc5

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-05-14 21:35:09 +02:00
commit 86e43a7aff
305 changed files with 3845 additions and 1898 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
Documentation/ABI/testing/sysfs-bus-hsi Normal file
View file

@ -0,0 +1,19 @@
What: /sys/bus/hsi
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description:
High Speed Synchronous Serial Interface (HSI) is a
serial interface mainly used for connecting application
engines (APE) with cellular modem engines (CMT) in cellular
handsets.
The bus will be populated with devices (hsi_clients) representing
the protocols available in the system. Bus drivers implement
those protocols.
What: /sys/bus/hsi/devices/.../modalias
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description: Stores the same MODALIAS value emitted by uevent
Format: hsi:<hsi_client device name>

40
Documentation/devicetree/bindings/arm/mrvl/intc.txt Normal file
View file

@ -0,0 +1,40 @@
* Marvell MMP Interrupt controller
Required properties:
- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
"mrvl,mmp2-mux-intc"
- reg : Address and length of the register set of the interrupt controller.
If the interrupt controller is intc, address and length means the range
of the whold interrupt controller. If the interrupt controller is mux-intc,
address and length means one register. Since address of mux-intc is in the
range of intc. mux-intc is secondary interrupt controller.
- reg-names : Name of the register set of the interrupt controller. It's
only required in mux-intc interrupt controller.
- interrupts : Should be the port interrupt shared by mux interrupts. It's
only required in mux-intc interrupt controller.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source.
- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
controller.
- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
detection first.
Example:
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
intcmux4@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};

8
Documentation/devicetree/bindings/arm/mrvl.txt → Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
View file

@ -4,3 +4,11 @@ Marvell Platforms Device Tree Bindings
PXA168 Aspenite Board
Required root node properties:
- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
PXA910 DKB Board
Required root node properties:
- compatible = "mrvl,pxa910-dkb";
MMP2 Brownstone Board
Required root node properties:
- compatible = "mrvl,mmp2-brownstone";

13
Documentation/devicetree/bindings/arm/mrvl/timer.txt Normal file
View file

@ -0,0 +1,13 @@
* Marvell MMP Timer controller
Required properties:
- compatible : Should be "mrvl,mmp-timer".
- reg : Address and length of the register set of timer controller.
- interrupts : Should be the interrupt number.
Example:
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};

18
Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
View file

@ -3,19 +3,25 @@
Required properties:
- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all gpio pins, if
- interrupt-name : Should be the name of irq resource.
one number.
- interrupts : Should be the port interrupt shared by all gpio pins.
There're three gpio interrupts in arch-pxa, and they're gpio0,
gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
gpio_mux.
- interrupt-name : Should be the name of irq resource. Each interrupt
binds its interrupt-name.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be one. It is the pin number.
Example:
gpio: gpio@d4019000 {
compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
compatible = "mrvl,mmp-gpio";
reg = <0xd4019000 0x1000>;
interrupts = <49>, <17>, <18>;
interrupt-name = "gpio_mux", "gpio0", "gpio1";
interrupts = <49>;
interrupt-name = "gpio_mux";
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;

15
Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
View file

@ -3,34 +3,31 @@
Required properties :
- reg : Offset and length of the register set for the device
- compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
- compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
as shown in the example below.
Recommended properties :
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupts : the interrupt number
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
services interrupts for this device. If the parent is the default
interrupt controller in device tree, it could be ignored.
- mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
status register of i2c controller instead.
- mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
Examples:
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
};

37
Documentation/power/freezing-of-tasks.txt
View file

@ -9,7 +9,7 @@ architectures).
II. How does it work?
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
PF_NOFREEZE unset (all user space processes and some kernel threads) are
regarded as 'freezable' and treated in a special way before the system enters a
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
we only consider hibernation, but the description also applies to suspend).
Namely, as the first step of the hibernation procedure the function
freeze_processes() (defined in kernel/power/process.c) is called. It executes
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
either wakes them up, if they are kernel threads, or sends fake signals to them,
if they are user space processes. A task that has TIF_FREEZE set, should react
to it by calling the function called __refrigerator() (defined in
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
Then, we say that the task is 'frozen' and therefore the set of functions
handling this mechanism is referred to as 'the freezer' (these functions are
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
User space processes are generally frozen before kernel threads.
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
whether the system is to undergo a freezing operation. And freeze_processes()
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
fake signal to all user space processes, and wakes up all the kernel threads.
All freezable tasks must react to that by calling try_to_freeze(), which
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
'frozen' and therefore the set of functions handling this mechanism is referred
to as 'the freezer' (these functions are defined in kernel/power/process.c,
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
frozen before kernel threads.
__refrigerator() must not be called directly. Instead, use the
try_to_freeze() function (defined in include/linux/freezer.h), that checks
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
flag is set.
if the task is to be frozen and makes the task enter __refrigerator().
For user space processes try_to_freeze() is called automatically from the
signal-handling code, but the freezable kernel threads need to call it
explicitly in suitable places or use the wait_event_freezable() or
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
try_to_freeze(). The main loop of a freezable kernel thread may look like the
following one:
that combine interruptible sleep with checking if the task is to be frozen and
calling try_to_freeze(). The main loop of a freezable kernel thread may look
like the following one:
set_freezable();
do {
@ -53,7 +54,7 @@ following one:
(from drivers/usb/core/hub.c::hub_thread()).
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
initiated a freezing operation, the freezing of tasks will fail and the entire
hibernation operation will be cancelled. For this reason, freezable kernel
threads must call try_to_freeze() somewhere or use one of the
wait_event_freezable() and wait_event_freezable_timeout() macros.

14
Documentation/security/keys.txt
View file

@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
The key service provides a number of features besides keys:
(*) The key service defines two special key types:
(*) The key service defines three special key types:
(+) "keyring"
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
blobs of data. These can be created, updated and read by userspace,
and aren't intended for use by kernel services.
(+) "logon"
Like a "user" key, a "logon" key has a payload that is an arbitrary
blob of data. It is intended as a place to store secrets which are
accessible to the kernel but not to userspace programs.
The description can be arbitrary, but must be prefixed with a non-zero
length string that describes the key "subclass". The subclass is
separated from the rest of the description by a ':'. "logon" keys can
be created and updated from userspace, but the payload is only
readable from kernel space.
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
process-specific keyring, and a session-specific keyring.

5
MAINTAINERS
View file

@ -3592,6 +3592,7 @@ S: Supported
F: drivers/net/wireless/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Johannes Berg <johannes.berg@intel.com>
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
@ -7578,8 +7579,8 @@ F: Documentation/filesystems/xfs.txt
F: fs/xfs/
XILINX AXI ETHERNET DRIVER
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
M: Anirudha Sarangi <anirudh@xilinx.com>
M: John Linn <John.Linn@xilinx.com>
S: Maintained
F: drivers/net/ethernet/xilinx/xilinx_axienet*

2
Makefile
View file

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 4
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*

1
arch/arm/Kconfig
View file

@ -633,6 +633,7 @@ config ARCH_MMP
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select GPIO_PXA
select IRQ_DOMAIN
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ

38
arch/arm/boot/dts/mmp2-brownstone.dts Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
/include/ "mmp2.dtsi"
/ {
model = "Marvell MMP2 Aspenite Development Board";
compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
chosen {
bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
};
memory {
reg = <0x00000000 0x04000000>;
};
soc {
apb@d4000000 {
uart3: uart@d4018000 {
status = "okay";
};
twsi1: i2c@d4011000 {
status = "okay";
};
rtc: rtc@d4010000 {
status = "okay";
};
};
};
};

220
arch/arm/boot/dts/mmp2.dtsi Normal file
View file

@ -0,0 +1,220 @@
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
i2c0 = &twsi1;
i2c1 = &twsi2;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
intcmux4@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
intcmux5: interrupt-controller@d4282154 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <5>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x154 0x4>, <0x16c 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
mrvl,clr-mfp-irq = <1>;
};
intcmux9: interrupt-controller@d4282180 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <9>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x180 0x4>, <0x17c 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <3>;
};
intcmux17: interrupt-controller@d4282158 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <17>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x158 0x4>, <0x170 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <5>;
};
intcmux35: interrupt-controller@d428215c {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <35>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x15c 0x4>, <0x174 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <15>;
};
intcmux51: interrupt-controller@d4282160 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <51>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x160 0x4>, <0x178 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
intcmux55: interrupt-controller@d4282188 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <55>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x188 0x4>, <0x184 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
uart1: uart@d4030000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4030000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4017000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4018000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <24>;
status = "disabled";
};
uart4: uart@d4016000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4016000 0x1000>;
interrupts = <46>;
status = "disabled";
};
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
gcb4: gpio@d4019104 {
reg = <0xd4019104 0x4>;
};
gcb5: gpio@d4019108 {
reg = <0xd4019108 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
status = "disabled";
};
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <1 0>;
interrupt-names = "rtc 1Hz", "rtc alarm";
interrupt-parent = <&intcmux5>;
status = "disabled";
};
};
};
};

4
arch/arm/boot/dts/msm8660-surf.dts
View file

@ -10,7 +10,7 @@
intc: interrupt-controller@02080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <3>;
reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >;
};
@ -19,6 +19,6 @@
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
interrupts = <0 195 0x0>;
};
};

67
arch/arm/boot/dts/pxa168.dtsi
View file

@ -18,13 +18,6 @@
i2c1 = &twsi2;
};
intc: intc-interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc", "mrvl,intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
@ -32,6 +25,23 @@
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
@ -39,40 +49,65 @@
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
uart1: uart@d4017000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4018000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4026000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4026000 0x1000>;
interrupts = <29>;
status = "disabled";
};
gpio: gpio@d4019000 {
compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
@ -80,7 +115,7 @@
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
status = "disabled";

38
arch/arm/boot/dts/pxa910-dkb.dts Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
/include/ "pxa910.dtsi"
/ {
model = "Marvell PXA910 DKB Development Board";
compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
};
memory {
reg = <0x00000000 0x10000000>;
};
soc {
apb@d4000000 {
uart1: uart@d4017000 {
status = "okay";
};
twsi1: i2c@d4011000 {
status = "okay";
};
rtc: rtc@d4010000 {
status = "okay";
};
};
};
};

140
arch/arm/boot/dts/pxa910.dtsi Normal file
View file

@ -0,0 +1,140 @@
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
i2c0 = &twsi1;
i2c1 = &twsi2;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
timer1: timer@d4016000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4016000 0x100>;
interrupts = <29>;
status = "disabled";
};
uart1: uart@d4017000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4018000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4036000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4036000 0x1000>;
interrupts = <59>;
status = "disabled";
};
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi2: i2c@d4037000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4037000 0x1000>;
interrupts = <54>;
status = "disabled";
};
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <5 6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
status = "disabled";
};
};
};
};

2
arch/arm/configs/mini2440_defconfig
View file

@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_ARCH_S3C24XX=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_S3C_ADC=y
CONFIG_S3C24XX_PWM=y
CONFIG_MACH_MINI2440=y

6
arch/arm/kernel/smp_twd.c
View file

@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
* The twd clock events must be reprogrammed to account for the new
* frequency. The timer is local to a cpu, so cross-call to the
* changing cpu.
*
* Only wait for it to finish, if the cpu is active to avoid
* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
* booting of that cpu.
*/
if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
smp_call_function_single(freqs->cpu, twd_update_frequency,
NULL, cpu_active(freqs->cpu));
NULL, 1);
return NOTIFY_OK;
}

24
arch/arm/mach-exynos/clock-exynos4.c
View file

@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

24
arch/arm/mach-exynos/clock-exynos5.c
View file

@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit = (1 << 20),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15),
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

14
arch/arm/mach-exynos/common.c
View file

@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
{
int irq;
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

13
arch/arm/mach-exynos/dev-dwmci.c
View file

@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
};
static struct dw_mci_board exynos4_dwci_pdata = {

1
arch/arm/mach-exynos/mach-nuri.c
View file

@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_ERASE),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};

1
arch/arm/mach-exynos/mach-universal_c210.c
View file

@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};

29
arch/arm/mach-mmp/Kconfig
View file

@ -2,16 +2,6 @@ if ARCH_MMP
menu "Marvell PXA168/910/MMP2 Implmentations"
config MACH_MMP_DT
bool "Support MMP2 platforms from device tree"
select CPU_PXA168
select CPU_PXA910
select USE_OF
help
Include support for Marvell MMP2 based platforms using
the device tree. Needn't select any other machine while
MACH_MMP_DT is enabled.
config MACH_ASPENITE
bool "Marvell's PXA168 Aspenite Development Board"
select CPU_PXA168
@ -94,6 +84,25 @@ config MACH_GPLUGD
Say 'Y' here if you want to support the Marvell PXA168-based
GuruPlug Display (gplugD) Board
config MACH_MMP_DT
bool "Support MMP (ARMv5) platforms from device tree"
select CPU_PXA168
select CPU_PXA910
select USE_OF
help
Include support for Marvell MMP2 based platforms using
the device tree. Needn't select any other machine while
MACH_MMP_DT is enabled.
config MACH_MMP2_DT
bool "Support MMP2 (ARMv7) platforms from device tree"
depends on !CPU_MOHAWK
select CPU_MMP2
select USE_OF
help
Include support for Marvell MMP2 based platforms using
the device tree.
endmenu
config CPU_PXA168

9
arch/arm/mach-mmp/Makefile
View file

@ -2,12 +2,12 @@
# Makefile for Marvell's PXA168 processors line
#
obj-y += common.o clock.o devices.o time.o
obj-y += common.o clock.o devices.o time.o irq.o
# SoC support
obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o
obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o
obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o sram.o
obj-$(CONFIG_CPU_PXA168) += pxa168.o
obj-$(CONFIG_CPU_PXA910) += pxa910.o
obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
# board support
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
@ -19,5 +19,6 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
obj-$(CONFIG_MACH_GPLUGD) += gplugd.o

4
arch/arm/mach-mmp/include/mach/entry-macro.S
View file

@ -6,13 +6,15 @@
* published by the Free Software Foundation.
*/
#include <asm/irq.h>
#include <mach/regs-icu.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
and \tmp, \tmp, #0xff00
cmp \tmp, #0x5800
ldr \base, =ICU_VIRT_BASE
ldr \base, =mmp_icu_base
ldr \base, [\base, #0]
addne \base, \base, #0x10c @ PJ1 AP INT SEL register
addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
.endm

27
arch/arm/mach-mmp/include/mach/irqs.h
View file

@ -125,7 +125,7 @@
#define IRQ_MMP2_RTC_MUX 5
#define IRQ_MMP2_TWSI1 7
#define IRQ_MMP2_GPU 8
#define IRQ_MMP2_KEYPAD 9
#define IRQ_MMP2_KEYPAD_MUX 9
#define IRQ_MMP2_ROTARY 10
#define IRQ_MMP2_TRACKBALL 11
#define IRQ_MMP2_ONEWIRE 12
@ -163,11 +163,11 @@
#define IRQ_MMP2_DMA_FIQ 47
#define IRQ_MMP2_DMA_RIQ 48
#define IRQ_MMP2_GPIO 49
#define IRQ_MMP2_SSP_MUX 51
#define IRQ_MMP2_MIPI_HSI1_MUX 51
#define IRQ_MMP2_MMC2 52
#define IRQ_MMP2_MMC3 53
#define IRQ_MMP2_MMC4 54
#define IRQ_MMP2_MIPI_HSI 55
#define IRQ_MMP2_MIPI_HSI0_MUX 55
#define IRQ_MMP2_MSP 58
#define IRQ_MMP2_MIPI_SLIM_DMA 59
#define IRQ_MMP2_PJ4_FREQ_CHG 60
@ -186,8 +186,14 @@
#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
/* secondary interrupt of INT #9 */
#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2)
#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0)
#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1)
#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2)
/* secondary interrupt of INT #17 */
#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2)
#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3)
#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
@ -212,11 +218,16 @@
#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
/* secondary interrupt of INT #51 */
#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15)
#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0)
#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1)
#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15)
#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0)
#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1)
#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2)
/* secondary interrupt of INT #55 */
#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2)
#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0)
#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1)
#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2)
#define IRQ_GPIO_START 128
#define MMP_NR_BUILTIN_GPIO 192

158
arch/arm/mach-mmp/irq-mmp2.c
View file

@ -1,158 +0,0 @@
/*
* linux/arch/arm/mach-mmp/irq-mmp2.c
*
* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
*
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
* Copyright: Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/irqs.h>
#include <mach/regs-icu.h>
#include <mach/mmp2.h>
#include "common.h"
static void icu_mask_irq(struct irq_data *d)
{
uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
r &= ~ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(d->irq));
}
static void icu_unmask_irq(struct irq_data *d)
{
uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
r |= ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(d->irq));
}
static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
.irq_mask = icu_mask_irq,
.irq_mask_ack = icu_mask_irq,
.irq_unmask = icu_unmask_irq,
};
static void pmic_irq_ack(struct irq_data *d)
{
if (d->irq == IRQ_MMP2_PMIC)
mmp2_clear_pmic_int();
}
#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
static void _name_##_mask_irq(struct irq_data *d) \
{ \
uint32_t r; \
r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
__raw_writel(r, prefix##_MASK); \
}
#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
static void _name_##_unmask_irq(struct irq_data *d) \
{ \
uint32_t r; \
r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
__raw_writel(r, prefix##_MASK); \
}
#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
{ \
unsigned long status, mask, n; \
mask = __raw_readl(prefix##_MASK); \
while (1) { \
status = __raw_readl(prefix##_STATUS) & ~mask; \
if (status == 0) \
break; \
n = find_first_bit(&status, BITS_PER_LONG); \
while (n < BITS_PER_LONG) { \
generic_handle_irq(irq_base + n); \
n = find_next_bit(&status, BITS_PER_LONG, n+1); \
} \
} \
}
#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
SECOND_IRQ_MASK(_name_, irq_base, prefix) \
SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
static struct irq_chip _name_##_irq_chip = { \
.name = #_name_, \
.irq_mask = _name_##_mask_irq, \
.irq_unmask = _name_##_unmask_irq, \
}
SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
static void init_mux_irq(struct irq_chip *chip, int start, int num)
{
int irq;
for (irq = start; num > 0; irq++, num--) {
struct irq_data *d = irq_get_irq_data(irq);
/* mask and clear the IRQ */
chip->irq_mask(d);
if (chip->irq_ack)
chip->irq_ack(d);
irq_set_chip(irq, chip);
set_irq_flags(irq, IRQF_VALID);
irq_set_handler(irq, handle_level_irq);
}
}
void __init mmp2_init_icu(void)
{
int irq;
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
irq_set_chip(irq, &icu_irq_chip);
set_irq_flags(irq, IRQF_VALID);
switch (irq) {
case IRQ_MMP2_PMIC_MUX:
case IRQ_MMP2_RTC_MUX:
case IRQ_MMP2_TWSI_MUX:
case IRQ_MMP2_MISC_MUX:
case IRQ_MMP2_SSP_MUX:
break;
default:
irq_set_handler(irq, handle_level_irq);
break;
}
}
/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
* to be written to clear the interrupt
*/
pmic_irq_chip.irq_ack = pmic_irq_ack;
init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
}

54
arch/arm/mach-mmp/irq-pxa168.c
View file

@ -1,54 +0,0 @@
/*
* linux/arch/arm/mach-mmp/irq.c
*
* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
*
* Author: Bin Yang <bin.yang@marvell.com>
* Created: Sep 30, 2008
* Copyright: Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/regs-icu.h>
#include "common.h"
#define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
#define PRIORITY_DEFAULT 0x1
#define PRIORITY_NONE 0x0 /* means IRQ disabled */
static void icu_mask_irq(struct irq_data *d)
{
__raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
}
static void icu_unmask_irq(struct irq_data *d)
{
__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
}
static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
.irq_ack = icu_mask_irq,
.irq_mask = icu_mask_irq,
.irq_unmask = icu_unmask_irq,
};
void __init icu_init_irq(void)
{
int irq;
for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}

445
arch/arm/mach-mmp/irq.c Normal file
View file

@ -0,0 +1,445 @@
/*
* linux/arch/arm/mach-mmp/irq.c
*
* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
* Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
*
* Author: Bin Yang <bin.yang@marvell.com>
* Haojian Zhuang <haojian.zhuang@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <mach/irqs.h>
#include "common.h"
#define MAX_ICU_NR 16
struct icu_chip_data {
int nr_irqs;
unsigned int virq_base;
unsigned int cascade_irq;
void __iomem *reg_status;
void __iomem *reg_mask;
unsigned int conf_enable;
unsigned int conf_disable;
unsigned int conf_mask;
unsigned int clr_mfp_irq_base;
unsigned int clr_mfp_hwirq;
struct irq_domain *domain;
};
struct mmp_intc_conf {
unsigned int conf_enable;
unsigned int conf_disable;
unsigned int conf_mask;
};
void __iomem *mmp_icu_base;
static struct icu_chip_data icu_data[MAX_ICU_NR];
static int max_icu_nr;
extern void mmp2_clear_pmic_int(void);
static void icu_mask_ack_irq(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
int hwirq;
u32 r;
hwirq = d->irq - data->virq_base;
if (data == &icu_data[0]) {
r = readl_relaxed(mmp_icu_base + (hwirq << 2));
r &= ~data->conf_mask;
r |= data->conf_disable;
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
} else {
#ifdef CONFIG_CPU_MMP2
if ((data->virq_base == data->clr_mfp_irq_base)
&& (hwirq == data->clr_mfp_hwirq))
mmp2_clear_pmic_int();
#endif
r = readl_relaxed(data->reg_mask) | (1 << hwirq);
writel_relaxed(r, data->reg_mask);
}
}
static void icu_mask_irq(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
int hwirq;
u32 r;
hwirq = d->irq - data->virq_base;
if (data == &icu_data[0]) {
r = readl_relaxed(mmp_icu_base + (hwirq << 2));
r &= ~data->conf_mask;
r |= data->conf_disable;
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
} else {
r = readl_relaxed(data->reg_mask) | (1 << hwirq);
writel_relaxed(r, data->reg_mask);
}
}
static void icu_unmask_irq(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
int hwirq;
u32 r;
hwirq = d->irq - data->virq_base;
if (data == &icu_data[0]) {
r = readl_relaxed(mmp_icu_base + (hwirq << 2));
r &= ~data->conf_mask;
r |= data->conf_enable;
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
} else {
r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
writel_relaxed(r, data->reg_mask);
}
}
static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
.irq_mask = icu_mask_irq,
.irq_mask_ack = icu_mask_ack_irq,
.irq_unmask = icu_unmask_irq,
};
static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
{
struct irq_domain *domain;
struct icu_chip_data *data;
int i;
unsigned long mask, status, n;
for (i = 1; i < max_icu_nr; i++) {
if (irq == icu_data[i].cascade_irq) {
domain = icu_data[i].domain;
data = (struct icu_chip_data *)domain->host_data;
break;
}
}
if (i >= max_icu_nr) {
pr_err("Spurious irq %d in MMP INTC\n", irq);
return;
}
mask = readl_relaxed(data->reg_mask);
while (1) {
status = readl_relaxed(data->reg_status) & ~mask;
if (status == 0)
break;
n = find_first_bit(&status, BITS_PER_LONG);
while (n < BITS_PER_LONG) {
generic_handle_irq(icu_data[i].virq_base + n);
n = find_next_bit(&status, BITS_PER_LONG, n + 1);
}
}
}
static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
return 0;
}
static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
*out_hwirq = intspec[0];
return 0;
}
const struct irq_domain_ops mmp_irq_domain_ops = {
.map = mmp_irq_domain_map,
.xlate = mmp_irq_domain_xlate,
};
static struct mmp_intc_conf mmp_conf = {
.conf_enable = 0x51,
.conf_disable = 0x0,
.conf_mask = 0x7f,
};
static struct mmp_intc_conf mmp2_conf = {
.conf_enable = 0x20,
.conf_disable = 0x0,
.conf_mask = 0x7f,
};
/* MMP (ARMv5) */
void __init icu_init_irq(void)
{
int irq;
max_icu_nr = 1;
mmp_icu_base = ioremap(0xd4282000, 0x1000);
icu_data[0].conf_enable = mmp_conf.conf_enable;
icu_data[0].conf_disable = mmp_conf.conf_disable;
icu_data[0].conf_mask = mmp_conf.conf_mask;
icu_data[0].nr_irqs = 64;
icu_data[0].virq_base = 0;
icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
&irq_domain_simple_ops,
&icu_data[0]);
for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
irq_set_default_host(icu_data[0].domain);
}
/* MMP2 (ARMv7) */
void __init mmp2_init_icu(void)
{
int irq;
max_icu_nr = 8;
mmp_icu_base = ioremap(0xd4282000, 0x1000);
icu_data[0].conf_enable = mmp2_conf.conf_enable;
icu_data[0].conf_disable = mmp2_conf.conf_disable;
icu_data[0].conf_mask = mmp2_conf.conf_mask;
icu_data[0].nr_irqs = 64;
icu_data[0].virq_base = 0;
icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
&irq_domain_simple_ops,
&icu_data[0]);
icu_data[1].reg_status = mmp_icu_base + 0x150;
icu_data[1].reg_mask = mmp_icu_base + 0x168;
icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
icu_data[1].nr_irqs = 2;
icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
icu_data[1].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[1]);
icu_data[2].reg_status = mmp_icu_base + 0x154;
icu_data[2].reg_mask = mmp_icu_base + 0x16c;
icu_data[2].nr_irqs = 2;
icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
icu_data[2].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[2]);
icu_data[3].reg_status = mmp_icu_base + 0x180;
icu_data[3].reg_mask = mmp_icu_base + 0x17c;
icu_data[3].nr_irqs = 3;
icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
icu_data[3].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[3]);
icu_data[4].reg_status = mmp_icu_base + 0x158;
icu_data[4].reg_mask = mmp_icu_base + 0x170;
icu_data[4].nr_irqs = 5;
icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
icu_data[4].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[4]);
icu_data[5].reg_status = mmp_icu_base + 0x15c;
icu_data[5].reg_mask = mmp_icu_base + 0x174;
icu_data[5].nr_irqs = 15;
icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
icu_data[5].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[5]);
icu_data[6].reg_status = mmp_icu_base + 0x160;
icu_data[6].reg_mask = mmp_icu_base + 0x178;
icu_data[6].nr_irqs = 2;
icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
icu_data[6].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[6]);
icu_data[7].reg_status = mmp_icu_base + 0x188;
icu_data[7].reg_mask = mmp_icu_base + 0x184;
icu_data[7].nr_irqs = 2;
icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
icu_data[7].virq_base, 0,
&irq_domain_simple_ops,
&icu_data[7]);
for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
switch (irq) {
case IRQ_MMP2_PMIC_MUX:
case IRQ_MMP2_RTC_MUX:
case IRQ_MMP2_KEYPAD_MUX:
case IRQ_MMP2_TWSI_MUX:
case IRQ_MMP2_MISC_MUX:
case IRQ_MMP2_MIPI_HSI1_MUX:
case IRQ_MMP2_MIPI_HSI0_MUX:
irq_set_chip(irq, &icu_irq_chip);
irq_set_chained_handler(irq, icu_mux_irq_demux);
break;
default:
irq_set_chip_and_handler(irq, &icu_irq_chip,
handle_level_irq);
break;
}
set_irq_flags(irq, IRQF_VALID);
}
irq_set_default_host(icu_data[0].domain);
}
#ifdef CONFIG_OF
static const struct of_device_id intc_ids[] __initconst = {
{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
{}
};
static const struct of_device_id mmp_mux_irq_match[] __initconst = {
{ .compatible = "mrvl,mmp2-mux-intc" },
{}
};
int __init mmp2_mux_init(struct device_node *parent)
{
struct device_node *node;
const struct of_device_id *of_id;
struct resource res;
int i, irq_base, ret, irq;
u32 nr_irqs, mfp_irq;
node = parent;
max_icu_nr = 1;
for (i = 1; i < MAX_ICU_NR; i++) {
node = of_find_matching_node(node, mmp_mux_irq_match);
if (!node)
break;
of_id = of_match_node(&mmp_mux_irq_match[0], node);
ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
&nr_irqs);
if (ret) {
pr_err("Not found mrvl,intc-nr-irqs property\n");
ret = -EINVAL;
goto err;
}
ret = of_address_to_resource(node, 0, &res);
if (ret < 0) {
pr_err("Not found reg property\n");
ret = -EINVAL;
goto err;
}
icu_data[i].reg_status = mmp_icu_base + res.start;
ret = of_address_to_resource(node, 1, &res);
if (ret < 0) {
pr_err("Not found reg property\n");
ret = -EINVAL;
goto err;
}
icu_data[i].reg_mask = mmp_icu_base + res.start;
icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
if (!icu_data[i].cascade_irq) {
ret = -EINVAL;
goto err;
}
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
if (irq_base < 0) {
pr_err("Failed to allocate IRQ numbers for mux intc\n");
ret = irq_base;
goto err;
}
if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
&mfp_irq)) {
icu_data[i].clr_mfp_irq_base = irq_base;
icu_data[i].clr_mfp_hwirq = mfp_irq;
}
irq_set_chained_handler(icu_data[i].cascade_irq,
icu_mux_irq_demux);
icu_data[i].nr_irqs = nr_irqs;
icu_data[i].virq_base = irq_base;
icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
irq_base, 0,
&mmp_irq_domain_ops,
&icu_data[i]);
for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
icu_mask_irq(irq_get_irq_data(irq));
}
max_icu_nr = i;
return 0;
err:
of_node_put(node);
max_icu_nr = i;
return ret;
}
void __init mmp_dt_irq_init(void)
{
struct device_node *node;
const struct of_device_id *of_id;
struct mmp_intc_conf *conf;
int nr_irqs, irq_base, ret, irq;
node = of_find_matching_node(NULL, intc_ids);
if (!node) {
pr_err("Failed to find interrupt controller in arch-mmp\n");
return;
}
of_id = of_match_node(intc_ids, node);
conf = of_id->data;
ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
if (ret) {
pr_err("Not found mrvl,intc-nr-irqs property\n");
return;
}
mmp_icu_base = of_iomap(node, 0);
if (!mmp_icu_base) {
pr_err("Failed to get interrupt controller register\n");
return;
}
irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
if (irq_base < 0) {
pr_err("Failed to allocate IRQ numbers\n");
goto err;
} else if (irq_base != NR_IRQS_LEGACY) {
pr_err("ICU's irqbase should be started from 0\n");
goto err;
}
icu_data[0].conf_enable = conf->conf_enable;
icu_data[0].conf_disable = conf->conf_disable;
icu_data[0].conf_mask = conf->conf_mask;
icu_data[0].nr_irqs = nr_irqs;
icu_data[0].virq_base = 0;
icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
&mmp_irq_domain_ops,
&icu_data[0]);
irq_set_default_host(icu_data[0].domain);
for (irq = 0; irq < nr_irqs; irq++)
icu_mask_irq(irq_get_irq_data(irq));
mmp2_mux_init(node);
return;
err:
iounmap(mmp_icu_base);
}
#endif

68
arch/arm/mach-mmp/mmp-dt.c
View file

@ -14,14 +14,19 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include "common.h"
extern struct sys_timer pxa168_timer;
extern void __init icu_init_irq(void);
extern void __init mmp_dt_irq_init(void);
extern void __init mmp_dt_init_timer(void);
static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
static struct sys_timer mmp_dt_timer = {
.init = mmp_dt_init_timer,
};
static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
@ -32,44 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
{}
};
static int __init mmp_intc_add_irq_domain(struct device_node *np,
struct device_node *parent)
{
irq_domain_add_simple(np, 0);
return 0;
}
static int __init mmp_gpio_add_irq_domain(struct device_node *np,
struct device_node *parent)
{
irq_domain_add_simple(np, IRQ_GPIO_START);
return 0;
}
static const struct of_device_id mmp_irq_match[] __initconst = {
{ .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
{ .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
{}
};
static void __init mmp_dt_init(void)
static void __init pxa168_dt_init(void)
{
of_irq_init(mmp_irq_match);
of_platform_populate(NULL, of_default_bus_match_table,
mmp_auxdata_lookup, NULL);
pxa168_auxdata_lookup, NULL);
}
static const char *pxa168_dt_board_compat[] __initdata = {
static void __init pxa910_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
pxa910_auxdata_lookup, NULL);
}
static const char *mmp_dt_board_compat[] __initdata = {
"mrvl,pxa168-aspenite",
"mrvl,pxa910-dkb",
NULL,
};
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = icu_init_irq,
.timer = &pxa168_timer,
.init_machine = mmp_dt_init,
.dt_compat = pxa168_dt_board_compat,
.init_irq = mmp_dt_irq_init,
.timer = &mmp_dt_timer,
.init_machine = pxa168_dt_init,
.dt_compat = mmp_dt_board_compat,
MACHINE_END
DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = mmp_dt_irq_init,
.timer = &mmp_dt_timer,
.init_machine = pxa910_dt_init,
.dt_compat = mmp_dt_board_compat,
MACHINE_END

60
arch/arm/mach-mmp/mmp2-dt.c Normal file
View file

@ -0,0 +1,60 @@
/*
* linux/arch/arm/mach-mmp/mmp2-dt.c
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include <mach/regs-apbc.h>
#include "common.h"
extern void __init mmp_dt_irq_init(void);
extern void __init mmp_dt_init_timer(void);
static struct sys_timer mmp_dt_timer = {
.init = mmp_dt_init_timer,
};
static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
{}
};
static void __init mmp2_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
mmp2_auxdata_lookup, NULL);
}
static const char *mmp2_dt_board_compat[] __initdata = {
"mrvl,mmp2-brownstone",
NULL,
};
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = mmp_dt_irq_init,
.timer = &mmp_dt_timer,
.init_machine = mmp2_dt_init,
.dt_compat = mmp2_dt_board_compat,
MACHINE_END

81
arch/arm/mach-mmp/time.c
View file

@ -25,6 +25,9 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/sched_clock.h>
#include <mach/addr-map.h>
@ -41,6 +44,8 @@
#define MAX_DELTA (0xfffffffe)
#define MIN_DELTA (16)
static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
/*
* FIXME: the timer needs some delay to stablize the counter capture
*/
@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
{
int delay = 100;
__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
while (delay--)
cpu_relax();
return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
return __raw_readl(mmp_timer_base + TMR_CVWR(1));
}
static u32 notrace mmp_read_sched_clock(void)
@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
/*
* Clear pending interrupt status.
*/
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
/*
* Disable timer 0.
*/
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
__raw_writel(0x02, mmp_timer_base + TMR_CER);
c->event_handler(c);
@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
/*
* Disable timer 0.
*/
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
__raw_writel(0x02, mmp_timer_base + TMR_CER);
/*
* Clear and enable timer match 0 interrupt.
*/
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
/*
* Setup new clockevent timer value.
*/
__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
/*
* Enable timer 0.
*/
__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
__raw_writel(0x03, mmp_timer_base + TMR_CER);
local_irq_restore(flags);
@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* disable the matching interrupt */
__raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
@ -157,27 +162,27 @@ static struct clocksource cksrc = {
static void __init timer_config(void)
{
uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
__raw_writel(ccr, mmp_timer_base + TMR_CCR);
/* set timer 0 to periodic mode, and timer 1 to free-running mode */
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
__raw_writel(0x2, mmp_timer_base + TMR_CMR);
__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
/* enable timer 1 counter */
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
__raw_writel(0x2, mmp_timer_base + TMR_CER);
}
static struct irqaction timer_irq = {
@ -203,3 +208,37 @@ void __init timer_init(int irq)
clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
clockevents_register_device(&ckevt);
}
#ifdef CONFIG_OF
static struct of_device_id mmp_timer_dt_ids[] = {
{ .compatible = "mrvl,mmp-timer", },
{}
};
void __init mmp_dt_init_timer(void)
{
struct device_node *np;
int irq, ret;
np = of_find_matching_node(NULL, mmp_timer_dt_ids);
if (!np) {
ret = -ENODEV;
goto out;
}
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
ret = -EINVAL;
goto out;
}
mmp_timer_base = of_iomap(np, 0);
if (!mmp_timer_base) {
ret = -ENOMEM;
goto out;
}
timer_init(irq);
return;
out:
pr_err("Failed to get timer from device tree with error:%d\n", ret);
}
#endif

25
arch/arm/mach-msm/board-msm8x60.c
View file

@ -17,6 +17,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
msm_map_msm8x60_io();
}
#ifdef CONFIG_OF
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
{}
};
#endif
static void __init msm8x60_init_irq(void)
{
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
if (!of_have_populated_dt())
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
#ifdef CONFIG_OF
else
of_irq_init(msm_dt_gic_match);
#endif
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
{}
};
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", },
{}
};
static void __init msm8x60_dt_init(void)
{
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
GIC_SPI_START);
if (of_machine_is_compatible("qcom,msm8660-surf")) {
printk(KERN_INFO "Init surf UART registers\n");
msm8x60_init_uart12dm();

7
arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
View file

@ -17,6 +17,7 @@
*
* bit 23 - Input/Output (PXA2xx specific)
* bit 24 - Wakeup Enable(PXA2xx specific)
* bit 25 - Keep Output (PXA2xx specific)
*/
#define MFP_DIR_IN (0x0 << 23)
@ -25,6 +26,12 @@
#define MFP_DIR(x) (((x) >> 23) & 0x1)
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
/*
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
* retain their last output level (low or high).
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
*/
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)

21
arch/arm/mach-pxa/mfp-pxa2xx.c
View file

@ -33,6 +33,8 @@
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
#define PWER_WE35 (1 << 24)
@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
#ifdef CONFIG_PM
static unsigned long saved_gafr[2][4];
static unsigned long saved_gpdr[4];
static unsigned long saved_gplr[4];
static unsigned long saved_pgsr[4];
static int pxa2xx_mfp_suspend(void)
@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
}
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
saved_gafr[0][i] = GAFR_L(i);
saved_gafr[1][i] = GAFR_U(i);
saved_gpdr[i] = GPDR(i * 32);
saved_gplr[i] = GPLR(i * 32);
saved_pgsr[i] = PGSR(i);
GPDR(i * 32) = gpdr_lpm[i];
GPSR(i * 32) = PGSR(i);
GPCR(i * 32) = ~PGSR(i);
}
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
for (i = 0; i < pxa_last_gpio; i++) {
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
GPDR(i) |= GPIO_bit(i);
else
GPDR(i) &= ~GPIO_bit(i);
}
return 0;
}
@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
GAFR_L(i) = saved_gafr[0][i];
GAFR_U(i) = saved_gafr[1][i];
GPSR(i * 32) = saved_gplr[i];
GPCR(i * 32) = ~saved_gplr[i];
GPDR(i * 32) = saved_gpdr[i];
PGSR(i) = saved_pgsr[i];
}

6
arch/arm/mach-pxa/pxa27x.c
View file

@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
pxa_register_device(&pxa27x_device_i2c_power, info);
}
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
.gpio_set_wake = gpio_set_wake,
};
static struct platform_device *devices[] __initdata = {
&pxa_device_gpio,
&pxa27x_device_udc,
&pxa_device_pmu,
&pxa_device_i2s,
@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
}

8
arch/arm/mach-s3c24xx/Kconfig
View file

@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
help
Compile in platform device definition for Samsung TouchScreen.
# cpu-specific sections
if CPU_S3C2410
config S3C2410_DMA
bool
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@ -127,6 +123,10 @@ config S3C2410_PM
help
Power Management code common to S3C2410 and better
# cpu-specific sections
if CPU_S3C2410
config S3C24XX_SIMTEC_NOR
bool
help

2
arch/arm/mach-s5pv210/mach-goni.c
View file

@ -25,6 +25,7 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/interrupt.h>
#include <asm/hardware/vic.h>
@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
/* MoviNAND */
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
.max_width = 4,
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};

2
arch/arm/mach-sa1100/generic.c
View file

@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
}
static struct resource sa1100_rtc_resources[] = {
DEFINE_RES_MEM(0x90010000, 0x9001003f),
DEFINE_RES_MEM(0x90010000, 0x40),
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};

6
arch/arm/mach-u300/core.c
View file

@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
for (i = 0; i < U300_VIC_IRQS_END; i++)
set_bit(i, (unsigned long *) &mask[0]);
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
mask[1], mask[1]);
}

9
arch/arm/mach-u300/i2c.c
View file

@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1,
.boot_on = 1,
},
@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 2500000,
.max_uV = 2500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1,
.boot_on = 1,
},
@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
},

150
arch/arm/mach-u300/include/mach/irqs.h
View file

@ -12,101 +12,101 @@
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_U300_INTCON0_START 0
#define IRQ_U300_INTCON1_START 32
#define IRQ_U300_INTCON0_START 1
#define IRQ_U300_INTCON1_START 33
/* These are on INTCON0 - 30 lines */
#define IRQ_U300_IRQ0_EXT 0
#define IRQ_U300_IRQ1_EXT 1
#define IRQ_U300_DMA 2
#define IRQ_U300_VIDEO_ENC_0 3
#define IRQ_U300_VIDEO_ENC_1 4
#define IRQ_U300_AAIF_RX 5
#define IRQ_U300_AAIF_TX 6
#define IRQ_U300_AAIF_VGPIO 7
#define IRQ_U300_AAIF_WAKEUP 8
#define IRQ_U300_PCM_I2S0_FRAME 9
#define IRQ_U300_PCM_I2S0_FIFO 10
#define IRQ_U300_PCM_I2S1_FRAME 11
#define IRQ_U300_PCM_I2S1_FIFO 12
#define IRQ_U300_XGAM_GAMCON 13
#define IRQ_U300_XGAM_CDI 14
#define IRQ_U300_XGAM_CDICON 15
#define IRQ_U300_IRQ0_EXT 1
#define IRQ_U300_IRQ1_EXT 2
#define IRQ_U300_DMA 3
#define IRQ_U300_VIDEO_ENC_0 4
#define IRQ_U300_VIDEO_ENC_1 5
#define IRQ_U300_AAIF_RX 6
#define IRQ_U300_AAIF_TX 7
#define IRQ_U300_AAIF_VGPIO 8
#define IRQ_U300_AAIF_WAKEUP 9
#define IRQ_U300_PCM_I2S0_FRAME 10
#define IRQ_U300_PCM_I2S0_FIFO 11
#define IRQ_U300_PCM_I2S1_FRAME 12
#define IRQ_U300_PCM_I2S1_FIFO 13
#define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 16
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
/* MMIACC not used on the DB3210 or DB3350 chips */
#define IRQ_U300_XGAM_MMIACC 16
#define IRQ_U300_XGAM_MMIACC 17
#endif
#define IRQ_U300_XGAM_PDI 17
#define IRQ_U300_XGAM_PDICON 18
#define IRQ_U300_XGAM_GAMEACC 19
#define IRQ_U300_XGAM_MCIDCT 20
#define IRQ_U300_APEX 21
#define IRQ_U300_UART0 22
#define IRQ_U300_SPI 23
#define IRQ_U300_TIMER_APP_OS 24
#define IRQ_U300_TIMER_APP_DD 25
#define IRQ_U300_TIMER_APP_GP1 26
#define IRQ_U300_TIMER_APP_GP2 27
#define IRQ_U300_TIMER_OS 28
#define IRQ_U300_TIMER_MS 29
#define IRQ_U300_KEYPAD_KEYBF 30
#define IRQ_U300_KEYPAD_KEYBR 31
#define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 20
#define IRQ_U300_XGAM_MCIDCT 21
#define IRQ_U300_APEX 22
#define IRQ_U300_UART0 23
#define IRQ_U300_SPI 24
#define IRQ_U300_TIMER_APP_OS 25
#define IRQ_U300_TIMER_APP_DD 26
#define IRQ_U300_TIMER_APP_GP1 27
#define IRQ_U300_TIMER_APP_GP2 28
#define IRQ_U300_TIMER_OS 29
#define IRQ_U300_TIMER_MS 30
#define IRQ_U300_KEYPAD_KEYBF 31
#define IRQ_U300_KEYPAD_KEYBR 32
/* These are on INTCON1 - 32 lines */
#define IRQ_U300_GPIO_PORT0 32
#define IRQ_U300_GPIO_PORT1 33
#define IRQ_U300_GPIO_PORT2 34
#define IRQ_U300_GPIO_PORT0 33
#define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 35
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 35
#define IRQ_U300_EVHIST 36
#define IRQ_U300_MSPRO 37
#define IRQ_U300_MMCSD_MCIINTR0 38
#define IRQ_U300_MMCSD_MCIINTR1 39
#define IRQ_U300_I2C0 40
#define IRQ_U300_I2C1 41
#define IRQ_U300_RTC 42
#define IRQ_U300_NFIF 43
#define IRQ_U300_NFIF2 44
#define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 37
#define IRQ_U300_MSPRO 38
#define IRQ_U300_MMCSD_MCIINTR0 39
#define IRQ_U300_MMCSD_MCIINTR1 40
#define IRQ_U300_I2C0 41
#define IRQ_U300_I2C1 42
#define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 45
#endif
/* DB3150 and DB3200 have only 45 IRQs */
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
#define U300_VIC_IRQS_END 45
#define U300_VIC_IRQS_END 46
#endif
/* The DB3350-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 45
#define IRQ_U300_ISP_F1 46
#define IRQ_U300_ISP_F2 47
#define IRQ_U300_ISP_F3 48
#define IRQ_U300_ISP_F4 49
#define IRQ_U300_GPIO_PORT3 50
#define IRQ_U300_SYSCON_PLL_LOCK 51
#define IRQ_U300_UART1 52
#define IRQ_U300_GPIO_PORT4 53
#define IRQ_U300_GPIO_PORT5 54
#define IRQ_U300_GPIO_PORT6 55
#define U300_VIC_IRQS_END 56
#define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 48
#define IRQ_U300_ISP_F3 49
#define IRQ_U300_ISP_F4 50
#define IRQ_U300_GPIO_PORT3 51
#define IRQ_U300_SYSCON_PLL_LOCK 52
#define IRQ_U300_UART1 53
#define IRQ_U300_GPIO_PORT4 54
#define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 57
#endif
/* The DB3210-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS365
#define IRQ_U300_GPIO_PORT3 35
#define IRQ_U300_GPIO_PORT4 36
#define IRQ_U300_WDOG 37
#define IRQ_U300_EVHIST 38
#define IRQ_U300_MSPRO 39
#define IRQ_U300_MMCSD_MCIINTR0 40
#define IRQ_U300_MMCSD_MCIINTR1 41
#define IRQ_U300_I2C0 42
#define IRQ_U300_I2C1 43
#define IRQ_U300_RTC 44
#define IRQ_U300_NFIF 45
#define IRQ_U300_NFIF2 46
#define IRQ_U300_SYSCON_PLL_LOCK 47
#define U300_VIC_IRQS_END 48
#define IRQ_U300_GPIO_PORT3 36
#define IRQ_U300_GPIO_PORT4 37
#define IRQ_U300_WDOG 38
#define IRQ_U300_EVHIST 39
#define IRQ_U300_MSPRO 40
#define IRQ_U300_MMCSD_MCIINTR0 41
#define IRQ_U300_MMCSD_MCIINTR1 42
#define IRQ_U300_I2C0 43
#define IRQ_U300_I2C1 44
#define IRQ_U300_RTC 45
#define IRQ_U300_NFIF 46
#define IRQ_U300_NFIF2 47
#define IRQ_U300_SYSCON_PLL_LOCK 48
#define U300_VIC_IRQS_END 49
#endif
/* Maximum 8*7 GPIO lines */
@ -117,6 +117,6 @@
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
#endif
#define NR_IRQS (IRQ_U300_GPIO_END)
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
#endif

2
arch/arm/mach-ux500/mbox-db5500.c
View file

@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
return sprintf(buf, "0x%X\n", mbox_value);
}
static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
static int mbox_show(struct seq_file *s, void *data)
{

28
arch/arm/plat-samsung/include/plat/sdhci.h
View file

@ -18,6 +18,8 @@
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
#include <plat/devs.h>
struct platform_device;
struct mmc_host;
struct mmc_card;
@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
static inline void s3c_sdhci_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S3C_DEV_HSMMC
case 0:
s3c_device_hsmmc0.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC1
case 1:
s3c_device_hsmmc1.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC2
case 2:
s3c_device_hsmmc2.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC3
case 3:
s3c_device_hsmmc3.name = name;
break;
#endif
}
}
#endif /* __PLAT_S3C_SDHCI_H */

53
arch/blackfin/mach-bf538/boards/ezkit.c
View file

@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#endif /* CONFIG_RTC_DRV_BFIN */
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_UART0 */
#ifdef CONFIG_SERIAL_BFIN_UART1
static struct resource bfin_uart1_resources[] = {
{
@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_UART1 */
#ifdef CONFIG_SERIAL_BFIN_UART2
static struct resource bfin_uart2_resources[] = {
{
@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
},
};
#endif
#endif
#endif /* CONFIG_SERIAL_BFIN_UART2 */
#endif /* CONFIG_SERIAL_BFIN */
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
.resource = bfin_sir0_resources,
};
#endif
#endif /* CONFIG_BFIN_SIR0 */
#ifdef CONFIG_BFIN_SIR1
static struct resource bfin_sir1_resources[] = {
{
@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
.resource = bfin_sir1_resources,
};
#endif
#endif /* CONFIG_BFIN_SIR1 */
#ifdef CONFIG_BFIN_SIR2
static struct resource bfin_sir2_resources[] = {
{
@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
.resource = bfin_sir2_resources,
};
#endif
#endif
#endif /* CONFIG_BFIN_SIR2 */
#endif /* CONFIG_BFIN_SIR */
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
static struct resource bfin_sport1_uart_resources[] = {
{
@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
static struct resource bfin_sport2_uart_resources[] = {
{
@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
static struct resource bfin_sport3_uart_resources[] = {
{
@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
},
};
#endif
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
#endif /* CONFIG_SERIAL_BFIN_SPORT */
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
static unsigned short bfin_can_peripherals[] = {
@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
.platform_data = &bfin_can_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_CAN_BFIN */
/*
* USB-LAN EzExtender board
@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
.platform_data = &smc91x_info,
},
};
#endif
#endif /* CONFIG_SMC91X */
#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
/* all SPI peripherals info goes here */
@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
static struct bfin5xx_spi_chip spi_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
};
#endif
#endif /* CONFIG_MTD_M25P80 */
#endif /* CONFIG_SPI_BFIN5XX */
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
#include <linux/spi/ad7879.h>
@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
.gpio_export = 1, /* Export GPIO to gpiolib */
.gpio_base = -1, /* Dynamic allocation */
};
#endif
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
#include <asm/bfin-lq035q1.h>
@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
.platform_data = &bfin_lq035q1_data,
},
};
#endif
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
static struct spi_board_info bf538_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
},
#endif
#endif /* CONFIG_MTD_M25P80 */
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
{
.modalias = "ad7879",
@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.chip_select = 1,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
{
.modalias = "bfin-lq035q1-spi",
@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.chip_select = 2,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.bus_num = 0,
.chip_select = 1,
},
#endif
#endif /* CONFIG_SPI_SPIDEV */
};
/* SPI (0) */
@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
},
};
#endif /* spi master and devices */
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
.resource = bfin_twi1_resource,
};
#endif
#endif
#endif /* CONFIG_BF542 */
#endif /* CONFIG_I2C_BLACKFIN_TWI */
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/gpio_keys.h>

1
arch/hexagon/kernel/dma.c
View file

@ -22,6 +22,7 @@
#include <linux/bootmem.h>
#include <linux/genalloc.h>
#include <asm/dma-mapping.h>
#include <linux/module.h>
struct dma_map_ops *dma_ops;
EXPORT_SYMBOL(dma_ops);

6
arch/hexagon/kernel/process.c
View file

@ -1,7 +1,7 @@
/*
* Process creation support for Hexagon
*
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
void cpu_idle(void)
{
while (1) {
tick_nohz_stop_sched_tick(1);
tick_nohz_idle_enter();
local_irq_disable();
while (!need_resched()) {
idle_sleep();
@ -97,7 +97,7 @@ void cpu_idle(void)
local_irq_disable();
}
local_irq_enable();
tick_nohz_restart_sched_tick();
tick_nohz_idle_exit();
schedule();
}
}

1
arch/hexagon/kernel/ptrace.c
View file

@ -28,6 +28,7 @@
#include <linux/ptrace.h>
#include <linux/regset.h>
#include <linux/user.h>
#include <linux/elf.h>
#include <asm/user.h>

8
arch/hexagon/kernel/smp.c
View file

@ -1,7 +1,7 @@
/*
* SMP support for Hexagon
*
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -28,6 +28,7 @@
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/cpu.h>
#include <asm/time.h> /* timer_interrupt */
#include <asm/hexagon_vm.h>
@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
notify_cpu_starting(cpu);
ipi_call_lock();
set_cpu_online(cpu, true);
ipi_call_unlock();
local_irq_enable();
cpu_idle();

1
arch/hexagon/kernel/time.c
View file

@ -28,6 +28,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/module.h>
#include <asm/timer-regs.h>
#include <asm/hexagon_vm.h>

1
arch/hexagon/kernel/vdso.c
View file

@ -21,6 +21,7 @@
#include <linux/err.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/binfmts.h>
#include <asm/vdso.h>

43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi Normal file
View file

@ -0,0 +1,43 @@
/*
* PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
message@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
interrupts = <
0xb4 2 0 0
0xb5 2 0 0
0xb6 2 0 0
0xb7 2 0 0>;
};

10
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
View file

@ -53,6 +53,16 @@ timer@41100 {
3 0 3 0>;
};
message@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <
0xb0 2 0 0
0xb1 2 0 0
0xb2 2 0 0
0xb3 2 0 0>;
};
msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x80>;

18
arch/powerpc/include/asm/mpic.h
View file

@ -275,9 +275,6 @@ struct mpic
unsigned int isu_mask;
/* Number of sources */
unsigned int num_sources;
/* default senses array */
unsigned char *senses;
unsigned int senses_count;
/* vector numbers used for internal sources (ipi/timers) */
unsigned int ipi_vecs[4];
@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
phys_addr_t phys_addr);
/* Set default sense codes
*
* @mpic: controller
* @senses: array of sense codes
* @count: size of above array
*
* Optionally provide an array (indexed on hardware interrupt numbers
* for this MPIC) of default sense codes for the chip. Those are linux
* sense codes IRQ_TYPE_*
*
* The driver gets ownership of the pointer, don't dispose of it or
* anything like that. __init only.
*/
extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
/* Initialize the controller. After this has been called, none of the above
* should be called again for this mpic

1
arch/powerpc/include/asm/mpic_msgr.h
View file

@ -13,6 +13,7 @@
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/smp.h>
struct mpic_msgr {
u32 __iomem *base;

5
arch/powerpc/include/asm/reg_booke.h
View file

@ -15,11 +15,6 @@
#ifndef __ASM_POWERPC_REG_BOOKE_H__
#define __ASM_POWERPC_REG_BOOKE_H__
#ifdef CONFIG_BOOKE_WDT
extern u32 booke_wdt_enabled;
extern u32 booke_wdt_period;
#endif /* CONFIG_BOOKE_WDT */
/* Machine State Register (MSR) Fields */
#define MSR_GS (1<<28) /* Guest state */
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */

3
arch/powerpc/kernel/setup_32.c
View file

@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
}
#ifdef CONFIG_BOOKE_WDT
extern u32 booke_wdt_enabled;
extern u32 booke_wdt_period;
/* Checks wdt=x and wdt_period=xx command-line option */
notrace int __init early_parse_wdt(char *p)
{

6
arch/powerpc/platforms/85xx/common.c
View file

@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .compatible = "fsl,qe", },
{ .compatible = "fsl,cpm2", },
{ .compatible = "fsl,srio", },
/* So that the DMA channel nodes can be probed individually: */
{ .compatible = "fsl,eloplus-dma", },
/* For the PMC driver */
{ .compatible = "fsl,mpc8548-guts", },
/* Probably unnecessary? */
{ .compatible = "gpio-leds", },
{},
};

11
arch/powerpc/platforms/85xx/mpc85xx_mds.c
View file

@ -399,12 +399,6 @@ static int __init board_fixups(void)
machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);
static struct of_device_id mpc85xx_ids[] = {
{ .compatible = "fsl,mpc8548-guts", },
{ .compatible = "gpio-leds", },
{},
};
static int __init mpc85xx_publish_devices(void)
{
if (machine_is(mpc8568_mds))
@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
if (machine_is(mpc8569_mds))
simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
mpc85xx_common_publish_devices();
of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
return 0;
return mpc85xx_common_publish_devices();
}
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);

13
arch/powerpc/platforms/85xx/p1022_ds.c
View file

@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
pr_info("Freescale P1022 DS reference board\n");
}
static struct of_device_id __initdata p1022_ds_ids[] = {
/* So that the DMA channel nodes can be probed individually: */
{ .compatible = "fsl,eloplus-dma", },
{},
};
static int __init p1022_ds_publish_devices(void)
{
mpc85xx_common_publish_devices();
return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
}
machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);

9
arch/powerpc/platforms/powermac/low_i2c.c
View file

@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
unsigned long flags;
spin_lock_irqsave(&host->lock, flags);
/*
* If the timer is pending, that means we raced with the
* irq, in which case we just return
*/
if (timer_pending(&host->timeout_timer))
goto skip;
kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
if (host->state != state_idle) {
host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
add_timer(&host->timeout_timer);
}
skip:
spin_unlock_irqrestore(&host->lock, flags);
}

2
arch/powerpc/platforms/pseries/eeh.c
View file

@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
pr_debug("EEH: Adding device %s\n", pci_name(dev));
dn = pci_device_to_OF_node(dev);
edev = pci_dev_to_eeh_dev(dev);
edev = of_node_to_eeh_dev(dn);
if (edev->pdev == dev) {
pr_debug("EEH: Already referenced !\n");
return;

56
arch/powerpc/sysdev/mpic.c
View file

@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
}
/* Determine if the linux irq is an IPI */
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
{
unsigned int src = virq_to_hw(irq);
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
}
/* Determine if the linux irq is a timer */
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
{
unsigned int src = virq_to_hw(irq);
return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
}
@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
if (src >= mpic->num_sources)
return -EINVAL;
if (flow_type == IRQ_TYPE_NONE)
if (mpic->senses && src < mpic->senses_count)
flow_type = mpic->senses[src];
if (flow_type == IRQ_TYPE_NONE)
flow_type = IRQ_TYPE_LEVEL_LOW;
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
/* We don't support "none" type */
if (flow_type == IRQ_TYPE_NONE)
flow_type = IRQ_TYPE_DEFAULT;
/* Default: read HW settings */
if (flow_type == IRQ_TYPE_DEFAULT) {
switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
MPIC_INFO(VECPRI_SENSE_MASK))) {
case MPIC_INFO(VECPRI_SENSE_EDGE) |
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
flow_type = IRQ_TYPE_EDGE_RISING;
break;
case MPIC_INFO(VECPRI_SENSE_EDGE) |
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
flow_type = IRQ_TYPE_EDGE_FALLING;
break;
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
flow_type = IRQ_TYPE_LEVEL_HIGH;
break;
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
flow_type = IRQ_TYPE_LEVEL_LOW;
break;
}
}
/* Apply to irq desc */
irqd_set_trigger_type(d, flow_type);
/* Apply to HW */
if (mpic_is_ht_interrupt(mpic, src))
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
MPIC_VECPRI_SENSE_EDGE;
else
vecpri = mpic_type_to_vecpri(mpic, flow_type);
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
MPIC_INFO(VECPRI_SENSE_MASK));
vnew |= vecpri;
@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
/* Set default irq type */
irq_set_irq_type(virq, IRQ_TYPE_NONE);
irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
/* If the MPIC was reset, then all vectors have already been
* initialized. Otherwise, a per source lazy initialization
@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
mpic->num_sources = isu_first + mpic->isu_size;
}
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
{
mpic->senses = senses;
mpic->senses_count = count;
}
void __init mpic_init(struct mpic *mpic)
{
int i, cpu;
@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
return;
raw_spin_lock_irqsave(&mpic_lock, flags);
if (mpic_is_ipi(mpic, irq)) {
if (mpic_is_ipi(mpic, src)) {
reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
~MPIC_VECPRI_PRIORITY_MASK;
mpic_ipi_write(src - mpic->ipi_vecs[0],
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
} else if (mpic_is_tm(mpic, irq)) {
} else if (mpic_is_tm(mpic, src)) {
reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
~MPIC_VECPRI_PRIORITY_MASK;
mpic_tm_write(src - mpic->timer_vecs[0],

12
arch/powerpc/sysdev/mpic_msgr.c
View file

@ -27,6 +27,7 @@
static struct mpic_msgr **mpic_msgrs;
static unsigned int mpic_msgr_count;
static DEFINE_RAW_SPINLOCK(msgrs_lock);
static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
{
@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
if (reg_num >= mpic_msgr_count)
return ERR_PTR(-ENODEV);
raw_spin_lock_irqsave(&msgr->lock, flags);
if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
msgr = mpic_msgrs[reg_num];
raw_spin_lock_irqsave(&msgrs_lock, flags);
msgr = mpic_msgrs[reg_num];
if (msgr->in_use == MSGR_FREE)
msgr->in_use = MSGR_INUSE;
}
raw_spin_unlock_irqrestore(&msgr->lock, flags);
raw_spin_unlock_irqrestore(&msgrs_lock, flags);
return msgr;
}
@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
msgr->in_use = MSGR_FREE;
msgr->num = i;
raw_spin_lock_init(&msgr->lock);

1
arch/powerpc/sysdev/scom.c
View file

@ -22,6 +22,7 @@
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/debug.h>
#include <asm/prom.h>
#include <asm/scom.h>

2
arch/sh/include/asm/atomic.h
View file

@ -11,7 +11,7 @@
#include <linux/types.h>
#include <asm/cmpxchg.h>
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) (*(volatile int *)&(v)->counter)
#define atomic_set(v,i) ((v)->counter = (i))

2
arch/sh/mm/fault_32.c
View file

@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address)
pte_t *pte_k;
/* Make sure we are in vmalloc/module/P3 area: */
if (!(address >= VMALLOC_START && address < P3_ADDR_MAX))
if (!(address >= P3SEG && address < P3_ADDR_MAX))
return -1;
/*

4
arch/tile/include/asm/pci.h
View file

@ -47,8 +47,8 @@ struct pci_controller {
*/
#define PCI_DMA_BUS_IS_PHYS 1
int __devinit tile_pci_init(void);
int __devinit pcibios_init(void);
int __init tile_pci_init(void);
int __init pcibios_init(void);
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}

4
arch/tile/kernel/pci.c
View file

@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
*
* Returns the number of controllers discovered.
*/
int __devinit tile_pci_init(void)
int __init tile_pci_init(void)
{
int i;
@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
* The controllers have been set up by the time we get here, by a call to
* tile_pci_init.
*/
int __devinit pcibios_init(void)
int __init pcibios_init(void)
{
int i;

14
arch/x86/boot/compressed/head_32.S
View file

@ -33,6 +33,9 @@
__HEAD
ENTRY(startup_32)
#ifdef CONFIG_EFI_STUB
jmp preferred_addr
.balign 0x10
/*
* We don't need the return address, so set up the stack so
* efi_main() can find its arugments.
@ -41,12 +44,17 @@ ENTRY(startup_32)
call efi_main
cmpl $0, %eax
je preferred_addr
movl %eax, %esi
call 1f
jne 2f
1:
/* EFI init failed, so hang. */
hlt
jmp 1b
2:
call 3f
3:
popl %eax
subl $1b, %eax
subl $3b, %eax
subl BP_pref_address(%esi), %eax
add BP_code32_start(%esi), %eax
leal preferred_addr(%eax), %eax

22
arch/x86/boot/compressed/head_64.S
View file

@ -200,18 +200,28 @@ ENTRY(startup_64)
* entire text+data+bss and hopefully all of memory.
*/
#ifdef CONFIG_EFI_STUB
pushq %rsi
/*
* The entry point for the PE/COFF executable is 0x210, so only
* legacy boot loaders will execute this jmp.
*/
jmp preferred_addr
.org 0x210
mov %rcx, %rdi
mov %rdx, %rsi
call efi_main
popq %rsi
cmpq $0,%rax
je preferred_addr
movq %rax,%rsi
call 1f
cmpq $0,%rax
jne 2f
1:
/* EFI init failed, so hang. */
hlt
jmp 1b
2:
call 3f
3:
popq %rax
subq $1b, %rax
subq $3b, %rax
subq BP_pref_address(%rsi), %rax
add BP_code32_start(%esi), %eax
leaq preferred_addr(%rax), %rax

15
arch/x86/boot/tools/build.c
View file

@ -205,8 +205,13 @@ int main(int argc, char ** argv)
put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
#ifdef CONFIG_X86_32
/* Address of entry point */
put_unaligned_le32(i, &buf[pe_header + 0x28]);
/*
* Address of entry point.
*
* The EFI stub entry point is +16 bytes from the start of
* the .text section.
*/
put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
/* .text size */
put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
@ -217,9 +222,11 @@ int main(int argc, char ** argv)
/*
* Address of entry point. startup_32 is at the beginning and
* the 64-bit entry point (startup_64) is always 512 bytes
* after.
* after. The EFI stub entry point is 16 bytes after that, as
* the first instruction allows legacy loaders to jump over
* the EFI stub initialisation
*/
put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
/* .text size */
put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);

6
arch/x86/include/asm/posix_types.h
View file

@ -7,9 +7,9 @@
#else
# ifdef __i386__
# include "posix_types_32.h"
# elif defined(__LP64__)
# include "posix_types_64.h"
# else
# elif defined(__ILP32__)
# include "posix_types_x32.h"
# else
# include "posix_types_64.h"
# endif
#endif

2
arch/x86/include/asm/sigcontext.h
View file

@ -257,7 +257,7 @@ struct sigcontext {
__u64 oldmask;
__u64 cr2;
struct _fpstate __user *fpstate; /* zero when no FPU context */
#ifndef __LP64__
#ifdef __ILP32__
__u32 __fpstate_pad;
#endif
__u64 reserved1[8];

8
arch/x86/include/asm/siginfo.h
View file

@ -2,7 +2,13 @@
#define _ASM_X86_SIGINFO_H
#ifdef __x86_64__
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
# ifdef __ILP32__ /* x32 */
typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
# define __ARCH_SI_CLOCK_T __kernel_si_clock_t
# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8)))
# else /* x86-64 */
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
# endif
#endif
#include <asm-generic/siginfo.h>

6
arch/x86/include/asm/unistd.h
View file

@ -63,10 +63,10 @@
#else
# ifdef __i386__
# include <asm/unistd_32.h>
# elif defined(__LP64__)
# include <asm/unistd_64.h>
# else
# elif defined(__ILP32__)
# include <asm/unistd_x32.h>
# else
# include <asm/unistd_64.h>
# endif
#endif

1
arch/x86/include/asm/x86_init.h
View file

@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi;
extern void x86_init_noop(void);
extern void x86_init_uint_noop(unsigned int unused);
extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
#endif

4
arch/x86/kernel/acpi/sleep.c
View file

@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
static char temp_stack[4096];
#endif
asmlinkage void acpi_enter_s3(void)
{
acpi_enter_sleep_state(3, wake_sleep_flags);
}
/**
* acpi_suspend_lowlevel - save kernel state
*

4
arch/x86/kernel/acpi/sleep.h
View file

@ -3,12 +3,16 @@
*/
#include <asm/trampoline.h>
#include <linux/linkage.h>
extern unsigned long saved_video_mode;
extern long saved_magic;
extern int wakeup_pmode_return;
extern u8 wake_sleep_flags;
extern asmlinkage void acpi_enter_s3(void);
extern unsigned long acpi_copy_wakeup_routine(unsigned long);
extern void wakeup_long64(void);

4
arch/x86/kernel/acpi/wakeup_32.S
View file

@ -74,9 +74,7 @@ restore_registers:
ENTRY(do_suspend_lowlevel)
call save_processor_state
call save_registers
pushl $3
call acpi_enter_sleep_state
addl $4, %esp
call acpi_enter_s3
# In case of S3 failure, we'll emerge here. Jump
# to ret_point to recover

4
arch/x86/kernel/acpi/wakeup_64.S
View file

@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
movq %rsi, saved_rsi
addq $8, %rsp
movl $3, %edi
xorl %eax, %eax
call acpi_enter_sleep_state
call acpi_enter_s3
/* in case something went wrong, restore the machine status and go on */
jmp resume_point

34
arch/x86/kernel/apic/apic.c
View file

@ -1637,9 +1637,11 @@ static int __init apic_verify(void)
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
/* The BIOS may have set up the APIC at some other address */
rdmsr(MSR_IA32_APICBASE, l, h);
if (l & MSR_IA32_APICBASE_ENABLE)
mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
if (l & MSR_IA32_APICBASE_ENABLE)
mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
}
pr_info("Found and enabled local APIC!\n");
return 0;
@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr)
* MSR. This can only be done in software for Intel P6 or later
* and AMD K7 (Model > 1) or later.
*/
rdmsr(MSR_IA32_APICBASE, l, h);
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | addr;
wrmsr(MSR_IA32_APICBASE, l, h);
enabled_via_apicbase = 1;
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | addr;
wrmsr(MSR_IA32_APICBASE, l, h);
enabled_via_apicbase = 1;
}
}
return apic_verify();
}
@ -2209,10 +2213,12 @@ static void lapic_resume(void)
* FIXME! This will be wrong if we ever support suspend on
* SMP! We'll need to do this as part of the CPU restore!
*/
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsr(MSR_IA32_APICBASE, l, h);
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsr(MSR_IA32_APICBASE, l, h);
}
}
maxlvt = lapic_get_maxlvt();

7
arch/x86/kernel/apic/apic_numachip.c
View file

@ -207,8 +207,11 @@ static void __init map_csrs(void)
static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
{
c->phys_proc_id = node;
per_cpu(cpu_llc_id, smp_processor_id()) = node;
if (c->phys_proc_id != node) {
c->phys_proc_id = node;
per_cpu(cpu_llc_id, smp_processor_id()) = node;
}
}
static int __init numachip_system_init(void)

6
arch/x86/kernel/apic/x2apic_phys.c
View file

@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
if (x2apic_phys)
return x2apic_enabled();
else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
x2apic_enabled()) {
printk(KERN_DEBUG "System requires x2apic physical mode\n");
return 1;
}
else
return 0;
}

11
arch/x86/kernel/cpu/amd.c
View file

@ -26,7 +26,8 @@
* contact AMD for precise details and a CPU swap.
*
* See http://www.multimania.com/poulot/k6bug.html
* http://www.amd.com/K6/k6docs/revgd.html
* and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
* (Publication # 21266 Issue Date: August 1998)
*
* The following test is erm.. interesting. AMD neglected to up
* the chip setting when fixing the bug but they also tweaked some
@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
"system stability may be impaired when more than 32 MB are used.\n");
else
printk(KERN_CONT "probably OK (after B9730xxxx).\n");
printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
}
/* K6 with old style WHCR */
@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
node = per_cpu(cpu_llc_id, cpu);
/*
* If core numbers are inconsistent, it's likely a multi-fabric platform,
* so invoke platform-specific handler
* On multi-fabric platform (e.g. Numascale NumaChip) a
* platform-specific handler needs to be called to fixup some
* IDs of the CPU.
*/
if (c->phys_proc_id != node)
if (x86_cpuinit.fixup_cpu_id)
x86_cpuinit.fixup_cpu_id(c, node);
if (!node_online(node)) {

9
arch/x86/kernel/cpu/common.c
View file

@ -1162,15 +1162,6 @@ static void dbg_restore_debug_regs(void)
#define dbg_restore_debug_regs()
#endif /* ! CONFIG_KGDB */
/*
* Prints an error where the NUMA and configured core-number mismatch and the
* platform didn't override this to fix it up
*/
void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
{
pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
}
/*
* cpu_init() initializes state that is per-CPU. Some data is already
* initialized (naturally) in the bootstrap process, such as the GDT

8
arch/x86/kernel/cpu/intel_cacheinfo.c
View file

@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
/* check if @slot is already used or the index is already disabled */
ret = amd_get_l3_disable_slot(nb, slot);
if (ret >= 0)
return -EINVAL;
return -EEXIST;
if (index > nb->l3_cache.indices)
return -EINVAL;
/* check whether the other slot has disabled the same index already */
if (index == amd_get_l3_disable_slot(nb, !slot))
return -EINVAL;
return -EEXIST;
amd_l3_disable_index(nb, cpu, slot, index);
@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
if (err) {
if (err == -EEXIST)
printk(KERN_WARNING "L3 disable slot %d in use!\n",
slot);
pr_warning("L3 slot %d in use/index already disabled!\n",
slot);
return err;
}
return count;

1
arch/x86/kernel/i387.c
View file

@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
if (tsk_used_math(tsk)) {
if (HAVE_HWFP && tsk == current)
unlazy_fpu(tsk);
tsk->thread.fpu.last_cpu = ~0;
return 0;
}

12
arch/x86/kernel/microcode_amd.c
View file

@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
struct cpuinfo_x86 *c = &cpu_data(cpu);
if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
return -1;
}
csig->rev = c->microcode;
pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
struct microcode_ops * __init init_amd_microcode(void)
{
struct cpuinfo_x86 *c = &cpu_data(0);
if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
return NULL;
}
patch = (void *)get_zeroed_page(GFP_KERNEL);
if (!patch)
return NULL;

10
arch/x86/kernel/microcode_core.c
View file

@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
if (err)
return err;
if (microcode_init_cpu(cpu) == UCODE_ERROR) {
sysfs_remove_group(&dev->kobj, &mc_attr_group);
if (microcode_init_cpu(cpu) == UCODE_ERROR)
return -EINVAL;
}
return err;
}
@ -528,11 +526,11 @@ static int __init microcode_init(void)
microcode_ops = init_intel_microcode();
else if (c->x86_vendor == X86_VENDOR_AMD)
microcode_ops = init_amd_microcode();
if (!microcode_ops) {
else
pr_err("no support for this CPU vendor\n");
if (!microcode_ops)
return -ENODEV;
}
microcode_pdev = platform_device_register_simple("microcode", -1,
NULL, 0);

1
arch/x86/kernel/x86_init.c
View file

@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = {
struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
.early_percpu_clock_init = x86_init_noop,
.setup_percpu_clockev = setup_secondary_APIC_clock,
.fixup_cpu_id = x86_default_fixup_cpu_id,
};
static void default_nmi_init(void) { };

4
arch/x86/platform/mrst/mrst.c
View file

@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
} else
i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
}
intel_scu_notifier_post(SCU_AVAILABLE, 0L);
intel_scu_notifier_post(SCU_AVAILABLE, NULL);
}
EXPORT_SYMBOL_GPL(intel_scu_devices_create);
@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
{
int i;
intel_scu_notifier_post(SCU_DOWN, 0L);
intel_scu_notifier_post(SCU_DOWN, NULL);
for (i = 0; i < ipc_next_dev; i++)
platform_device_del(ipc_devs[i]);

4
arch/x86/xen/enlighten.c
View file

@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
static bool __init xen_check_mwait(void)
{
#ifdef CONFIG_ACPI
#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
!defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
struct xen_platform_op op = {
.cmd = XENPF_set_processor_pminfo,
.u.set_pminfo.id = -1,
@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void)
/* Xen will set CR4.OSXSAVE if supported and not disabled by force */
if ((cx & xsave_mask) != xsave_mask)
cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
if (xen_check_mwait())
cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
}

15
arch/x86/xen/smp.c
View file

@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
static void __init xen_filter_cpu_maps(void)
{
int i, rc;
unsigned int subtract = 0;
if (!xen_initial_domain())
return;
@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
} else {
set_cpu_possible(i, false);
set_cpu_present(i, false);
subtract++;
}
}
#ifdef CONFIG_HOTPLUG_CPU
/* This is akin to using 'nr_cpus' on the Linux command line.
* Which is OK as when we use 'dom0_max_vcpus=X' we can only
* have up to X, while nr_cpu_ids is greater than X. This
* normally is not a problem, except when CPU hotplugging
* is involved and then there might be more than X CPUs
* in the guest - which will not work as there is no
* hypercall to expand the max number of VCPUs an already
* running guest has. So cap it up to X. */
if (subtract)
nr_cpu_ids = nr_cpu_ids - subtract;
#endif
}
static void __init xen_smp_prepare_boot_cpu(void)

2
arch/x86/xen/xen-asm.S
View file

@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
/* check for unmasked and pending */
cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
jz 1f
jnz 1f
2: call check_events
1:
ENDPATCH(xen_restore_fl_direct)

3
arch/xtensa/include/asm/hardirq.h
View file

@ -11,9 +11,6 @@
#ifndef _XTENSA_HARDIRQ_H
#define _XTENSA_HARDIRQ_H
void ack_bad_irq(unsigned int irq);
#define ack_bad_irq ack_bad_irq
#include <asm-generic/hardirq.h>
#endif /* _XTENSA_HARDIRQ_H */

1
arch/xtensa/include/asm/io.h
View file

@ -14,6 +14,7 @@
#ifdef __KERNEL__
#include <asm/byteorder.h>
#include <asm/page.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>

Some files were not shown because too many files have changed in this diff Show more