[SPARC64]: SUN4U PCI-E controller support.
Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
4cad69174f
commit
861fe90656
7 changed files with 535 additions and 22 deletions
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@ -17,7 +17,7 @@ obj-y := process.o setup.o cpu.o idprom.o \
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obj-$(CONFIG_STACKTRACE) += stacktrace.o
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obj-$(CONFIG_PCI) += ebus.o isa.o pci_common.o pci_iommu.o \
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pci_psycho.o pci_sabre.o pci_schizo.o \
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pci_sun4v.o pci_sun4v_asm.o
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pci_sun4v.o pci_sun4v_asm.o pci_fire.o
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obj-$(CONFIG_SMP) += smp.o trampoline.o
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obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o
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obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o
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@ -279,7 +279,7 @@ static void sun4u_irq_enable(unsigned int virt_irq)
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struct irq_handler_data *data = get_irq_chip_data(virt_irq);
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if (likely(data)) {
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unsigned long cpuid, imap;
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unsigned long cpuid, imap, val;
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unsigned int tid;
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cpuid = irq_choose_cpu(virt_irq);
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@ -287,7 +287,11 @@ static void sun4u_irq_enable(unsigned int virt_irq)
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tid = sun4u_compute_tid(imap, cpuid);
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upa_writel(tid | IMAP_VALID, imap);
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val = upa_readq(imap);
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val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
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IMAP_AID_SAFARI | IMAP_NID_SAFARI);
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val |= tid | IMAP_VALID;
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upa_writeq(val, imap);
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}
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}
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@ -297,10 +301,10 @@ static void sun4u_irq_disable(unsigned int virt_irq)
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if (likely(data)) {
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unsigned long imap = data->imap;
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u32 tmp = upa_readl(imap);
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u32 tmp = upa_readq(imap);
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tmp &= ~IMAP_VALID;
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upa_writel(tmp, imap);
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upa_writeq(tmp, imap);
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}
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}
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@ -309,7 +313,7 @@ static void sun4u_irq_end(unsigned int virt_irq)
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struct irq_handler_data *data = get_irq_chip_data(virt_irq);
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if (likely(data))
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upa_writel(ICLR_IDLE, data->iclr);
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upa_writeq(ICLR_IDLE, data->iclr);
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}
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static void sun4v_irq_enable(unsigned int virt_irq)
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@ -465,7 +469,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
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BUG_ON(tlb_type == hypervisor);
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ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
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ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
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bucket = &ivector_table[ino];
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if (!bucket->virt_irq) {
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bucket->virt_irq = virt_irq_alloc(__irq(bucket));
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@ -190,6 +190,7 @@ extern void schizo_init(struct device_node *, const char *);
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extern void schizo_plus_init(struct device_node *, const char *);
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extern void tomatillo_init(struct device_node *, const char *);
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extern void sun4v_pci_init(struct device_node *, const char *);
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extern void fire_pci_init(struct device_node *, const char *);
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static struct {
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char *model_name;
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@ -207,6 +208,7 @@ static struct {
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{ "SUNW,tomatillo", tomatillo_init },
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{ "pci108e,a801", tomatillo_init },
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{ "SUNW,sun4v-pci", sun4v_pci_init },
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{ "pciex108e,80f0", fire_pci_init },
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};
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#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
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sizeof(pci_controller_table[0]))
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@ -436,6 +438,13 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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printk(" class: 0x%x device name: %s\n",
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dev->class, pci_name(dev));
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/* I have seen IDE devices which will not respond to
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* the bmdma simplex check reads if bus mastering is
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* disabled.
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*/
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
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pci_set_master(dev);
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dev->current_state = 4; /* unknown power state */
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dev->error_state = pci_channel_io_normal;
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418
arch/sparc64/kernel/pci_fire.c
Normal file
418
arch/sparc64/kernel/pci_fire.c
Normal file
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@ -0,0 +1,418 @@
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/* pci_fire.c: Sun4u platform PCI-E controller support.
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*
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* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <asm/pbm.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include "pci_impl.h"
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#define fire_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define fire_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory")
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/* Fire config space address format is nearly identical to
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* that of SCHIZO and PSYCHO, except that in order to accomodate
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* PCI-E extended config space the encoding can handle 12 bits
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* of register address:
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*
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* 32 28 27 20 19 15 14 12 11 2 1 0
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* -------------------------------------------------
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* |0 0 0 0 0| bus | device | function | reg | 0 0 |
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* -------------------------------------------------
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*/
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#define FIRE_CONFIG_BASE(PBM) ((PBM)->config_space)
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#define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
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(((unsigned long)(BUS) << 20) | \
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((unsigned long)(DEVFN) << 12) | \
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((unsigned long)(REG)))
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static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
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unsigned char bus,
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unsigned int devfn,
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int where)
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{
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if (!pbm)
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return NULL;
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return (void *)
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(FIRE_CONFIG_BASE(pbm) |
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FIRE_CONFIG_ENCODE(bus, devfn, where));
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}
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/* FIRE PCI configuration space accessors. */
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static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct pci_pbm_info *pbm = bus_dev->sysdata;
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unsigned char bus = bus_dev->number;
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u32 *addr;
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u16 tmp16;
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u8 tmp8;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
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size, value);
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switch (size) {
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case 1:
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*value = 0xff;
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break;
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case 2:
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*value = 0xffff;
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break;
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case 4:
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*value = 0xffffffff;
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break;
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}
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addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
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if (!addr)
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return PCIBIOS_SUCCESSFUL;
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switch (size) {
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case 1:
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pci_config_read8((u8 *)addr, &tmp8);
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*value = tmp8;
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break;
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case 2:
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if (where & 0x01) {
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printk("pci_read_config_word: misaligned reg [%x]\n",
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where);
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return PCIBIOS_SUCCESSFUL;
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}
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pci_config_read16((u16 *)addr, &tmp16);
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*value = tmp16;
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break;
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case 4:
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if (where & 0x03) {
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printk("pci_read_config_dword: misaligned reg [%x]\n",
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where);
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return PCIBIOS_SUCCESSFUL;
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}
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pci_config_read32(addr, value);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct pci_pbm_info *pbm = bus_dev->sysdata;
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unsigned char bus = bus_dev->number;
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u32 *addr;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
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size, value);
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addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
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if (!addr)
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return PCIBIOS_SUCCESSFUL;
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switch (size) {
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case 1:
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pci_config_write8((u8 *)addr, value);
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break;
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case 2:
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if (where & 0x01) {
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printk("pci_write_config_word: misaligned reg [%x]\n",
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where);
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return PCIBIOS_SUCCESSFUL;
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}
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pci_config_write16((u16 *)addr, value);
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break;
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case 4:
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if (where & 0x03) {
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printk("pci_write_config_dword: misaligned reg [%x]\n",
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where);
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return PCIBIOS_SUCCESSFUL;
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}
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pci_config_write32(addr, value);
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_fire_ops = {
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.read = fire_read_pci_cfg,
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.write = fire_write_pci_cfg,
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};
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static void pbm_scan_bus(struct pci_controller_info *p,
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struct pci_pbm_info *pbm)
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{
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pbm->pci_bus = pci_scan_one_pbm(pbm);
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}
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static void pci_fire_scan_bus(struct pci_controller_info *p)
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{
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struct device_node *dp;
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if ((dp = p->pbm_A.prom_node) != NULL)
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pbm_scan_bus(p, &p->pbm_A);
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if ((dp = p->pbm_B.prom_node) != NULL)
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pbm_scan_bus(p, &p->pbm_B);
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/* XXX register error interrupt handlers XXX */
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}
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#define FIRE_IOMMU_CONTROL 0x40000UL
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#define FIRE_IOMMU_TSBBASE 0x40008UL
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#define FIRE_IOMMU_FLUSH 0x40100UL
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#define FIRE_IOMMU_FLUSHINV 0x40100UL
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static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
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{
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struct iommu *iommu = pbm->iommu;
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u32 vdma[2], dma_mask;
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u64 control;
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int tsbsize;
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/* No virtual-dma property on these guys, use largest size. */
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vdma[0] = 0xc0000000; /* base */
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vdma[1] = 0x40000000; /* size */
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dma_mask = 0xffffffff;
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tsbsize = 128;
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/* Register addresses. */
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iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
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iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
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/* We use the main control/status register of FIRE as the write
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* completion register.
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*/
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iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
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/*
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* Invalidate TLB Entries.
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*/
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fire_write(iommu->iommu_flushinv, ~(u64)0);
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pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
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fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
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control = fire_read(iommu->iommu_control);
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control |= (0x00000400 /* TSB cache snoop enable */ |
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0x00000300 /* Cache mode */ |
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0x00000002 /* Bypass enable */ |
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0x00000001 /* Translation enable */);
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fire_write(iommu->iommu_control, control);
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}
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/* Based at pbm->controller_regs */
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#define FIRE_PARITY_CONTROL 0x470010UL
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#define FIRE_PARITY_ENAB 0x8000000000000000UL
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#define FIRE_FATAL_RESET_CTL 0x471028UL
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#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
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#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
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#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
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#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
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#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
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#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
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#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
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#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
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#define FIRE_CORE_INTR_ENABLE 0x471800UL
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/* Based at pbm->pbm_regs */
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#define FIRE_TLU_CTRL 0x80000UL
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#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
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#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
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#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
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#define FIRE_TLU_DEV_CTRL 0x90008UL
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#define FIRE_TLU_LINK_CTRL 0x90020UL
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#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
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#define FIRE_LPU_RESET 0xe2008UL
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#define FIRE_LPU_LLCFG 0xe2200UL
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#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
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#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
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#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
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#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
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#define FIRE_LPU_TXL_FIFOP 0xe2430UL
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#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
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#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
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#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
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#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
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#define FIRE_DMC_IENAB 0x31800UL
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#define FIRE_DMC_DBG_SEL_A 0x53000UL
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#define FIRE_DMC_DBG_SEL_B 0x53008UL
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#define FIRE_PEC_IENAB 0x51800UL
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static void pci_fire_hw_init(struct pci_pbm_info *pbm)
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{
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u64 val;
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fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
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FIRE_PARITY_ENAB);
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fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
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(FIRE_FATAL_RESET_SPARE |
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FIRE_FATAL_RESET_MB |
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FIRE_FATAL_RESET_CPE |
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FIRE_FATAL_RESET_APE |
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FIRE_FATAL_RESET_PIO |
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FIRE_FATAL_RESET_JW |
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FIRE_FATAL_RESET_JI |
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FIRE_FATAL_RESET_JR));
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fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
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val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
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val |= (FIRE_TLU_CTRL_TIM |
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FIRE_TLU_CTRL_QDET |
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FIRE_TLU_CTRL_CFG);
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fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
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fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
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fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
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FIRE_TLU_LINK_CTRL_CLK);
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fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
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fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
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FIRE_LPU_LLCFG_VC0);
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fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
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(FIRE_LPU_FCTRL_UCTRL_N |
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FIRE_LPU_FCTRL_UCTRL_P));
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fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
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((0xffff << 16) | (0x0000 << 0)));
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
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(2 << 16) | (140 << 8));
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
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fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
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fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
|
||||
fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
|
||||
|
||||
fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
|
||||
}
|
||||
|
||||
static void pci_fire_pbm_init(struct pci_controller_info *p,
|
||||
struct device_node *dp, u32 portid)
|
||||
{
|
||||
const struct linux_prom64_registers *regs;
|
||||
struct pci_pbm_info *pbm;
|
||||
const u32 *ino_bitmap;
|
||||
const unsigned int *busrange;
|
||||
|
||||
if ((portid & 1) == 0)
|
||||
pbm = &p->pbm_A;
|
||||
else
|
||||
pbm = &p->pbm_B;
|
||||
|
||||
pbm->portid = portid;
|
||||
pbm->parent = p;
|
||||
pbm->prom_node = dp;
|
||||
pbm->name = dp->full_name;
|
||||
|
||||
regs = of_get_property(dp, "reg", NULL);
|
||||
pbm->pbm_regs = regs[0].phys_addr;
|
||||
pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
|
||||
|
||||
printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
|
||||
|
||||
pci_determine_mem_io_space(pbm);
|
||||
|
||||
ino_bitmap = of_get_property(dp, "ino-bitmap", NULL);
|
||||
pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
|
||||
((u64)ino_bitmap[0] << 0UL));
|
||||
|
||||
busrange = of_get_property(dp, "bus-range", NULL);
|
||||
pbm->pci_first_busno = busrange[0];
|
||||
pbm->pci_last_busno = busrange[1];
|
||||
|
||||
pci_fire_hw_init(pbm);
|
||||
pci_fire_pbm_iommu_init(pbm);
|
||||
}
|
||||
|
||||
static inline int portid_compare(u32 x, u32 y)
|
||||
{
|
||||
if (x == (y ^ 1))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fire_pci_init(struct device_node *dp, const char *model_name)
|
||||
{
|
||||
struct pci_controller_info *p;
|
||||
u32 portid = of_getintprop_default(dp, "portid", 0xff);
|
||||
struct iommu *iommu;
|
||||
|
||||
for (p = pci_controller_root; p; p = p->next) {
|
||||
struct pci_pbm_info *pbm;
|
||||
|
||||
if (p->pbm_A.prom_node && p->pbm_B.prom_node)
|
||||
continue;
|
||||
|
||||
pbm = (p->pbm_A.prom_node ?
|
||||
&p->pbm_A :
|
||||
&p->pbm_B);
|
||||
|
||||
if (portid_compare(pbm->portid, portid)) {
|
||||
pci_fire_pbm_init(p, dp, portid);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
|
||||
if (!p)
|
||||
goto fatal_memory_error;
|
||||
|
||||
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
||||
if (!iommu)
|
||||
goto fatal_memory_error;
|
||||
|
||||
p->pbm_A.iommu = iommu;
|
||||
|
||||
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
||||
if (!iommu)
|
||||
goto fatal_memory_error;
|
||||
|
||||
p->pbm_B.iommu = iommu;
|
||||
|
||||
p->next = pci_controller_root;
|
||||
pci_controller_root = p;
|
||||
|
||||
p->index = pci_num_controllers++;
|
||||
|
||||
p->scan_bus = pci_fire_scan_bus;
|
||||
/* XXX MSI support XXX */
|
||||
p->pci_ops = &pci_fire_ops;
|
||||
|
||||
/* Like PSYCHO and SCHIZO we have a 2GB aligned area
|
||||
* for memory space.
|
||||
*/
|
||||
pci_memspace_mask = 0x7fffffffUL;
|
||||
|
||||
pci_fire_pbm_init(p, dp, portid);
|
||||
return;
|
||||
|
||||
fatal_memory_error:
|
||||
prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
|
||||
prom_halt();
|
||||
}
|
||||
|
|
@ -37,17 +37,21 @@
|
|||
/* Must be invoked under the IOMMU lock. */
|
||||
static void __iommu_flushall(struct iommu *iommu)
|
||||
{
|
||||
unsigned long tag;
|
||||
int entry;
|
||||
if (iommu->iommu_flushinv) {
|
||||
pci_iommu_write(iommu->iommu_flushinv, ~(u64)0);
|
||||
} else {
|
||||
unsigned long tag;
|
||||
int entry;
|
||||
|
||||
tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
|
||||
for (entry = 0; entry < 16; entry++) {
|
||||
pci_iommu_write(tag, 0);
|
||||
tag += 8;
|
||||
tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
|
||||
for (entry = 0; entry < 16; entry++) {
|
||||
pci_iommu_write(tag, 0);
|
||||
tag += 8;
|
||||
}
|
||||
|
||||
/* Ensure completion of previous PIO writes. */
|
||||
(void) pci_iommu_read(iommu->write_complete_reg);
|
||||
}
|
||||
|
||||
/* Ensure completion of previous PIO writes. */
|
||||
(void) pci_iommu_read(iommu->write_complete_reg);
|
||||
}
|
||||
|
||||
#define IOPTE_CONSISTENT(CTX) \
|
||||
|
|
|
|||
|
|
@ -386,11 +386,9 @@ static unsigned int psycho_irq_build(struct device_node *dp,
|
|||
|
||||
/* Now build the IRQ bucket. */
|
||||
imap = controller_regs + imap_off;
|
||||
imap += 4;
|
||||
|
||||
iclr_off = psycho_iclr_offset(ino);
|
||||
iclr = controller_regs + iclr_off;
|
||||
iclr += 4;
|
||||
|
||||
if ((ino & 0x20) == 0)
|
||||
inofixup = ino & 0x03;
|
||||
|
|
@ -613,11 +611,9 @@ static unsigned int sabre_irq_build(struct device_node *dp,
|
|||
|
||||
/* Now build the IRQ bucket. */
|
||||
imap = controller_regs + imap_off;
|
||||
imap += 4;
|
||||
|
||||
iclr_off = sabre_iclr_offset(ino);
|
||||
iclr = controller_regs + iclr_off;
|
||||
iclr += 4;
|
||||
|
||||
if ((ino & 0x20) == 0)
|
||||
inofixup = ino & 0x03;
|
||||
|
|
@ -679,13 +675,14 @@ static unsigned long schizo_iclr_offset(unsigned long ino)
|
|||
static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
|
||||
unsigned int ino)
|
||||
{
|
||||
return pbm_regs + schizo_iclr_offset(ino) + 4;
|
||||
|
||||
return pbm_regs + schizo_iclr_offset(ino);
|
||||
}
|
||||
|
||||
static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
|
||||
unsigned int ino)
|
||||
{
|
||||
return pbm_regs + schizo_imap_offset(ino) + 4;
|
||||
return pbm_regs + schizo_imap_offset(ino);
|
||||
}
|
||||
|
||||
#define schizo_read(__reg) \
|
||||
|
|
@ -848,6 +845,85 @@ static void pci_sun4v_irq_trans_init(struct device_node *dp)
|
|||
dp->irq_trans->data = (void *) (unsigned long)
|
||||
((regs->phys_addr >> 32UL) & 0x0fffffff);
|
||||
}
|
||||
|
||||
struct fire_irq_data {
|
||||
unsigned long pbm_regs;
|
||||
u32 portid;
|
||||
};
|
||||
|
||||
#define FIRE_IMAP_BASE 0x001000
|
||||
#define FIRE_ICLR_BASE 0x001400
|
||||
|
||||
static unsigned long fire_imap_offset(unsigned long ino)
|
||||
{
|
||||
return FIRE_IMAP_BASE + (ino * 8UL);
|
||||
}
|
||||
|
||||
static unsigned long fire_iclr_offset(unsigned long ino)
|
||||
{
|
||||
return FIRE_ICLR_BASE + (ino * 8UL);
|
||||
}
|
||||
|
||||
static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
|
||||
unsigned int ino)
|
||||
{
|
||||
return pbm_regs + fire_iclr_offset(ino);
|
||||
}
|
||||
|
||||
static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
|
||||
unsigned int ino)
|
||||
{
|
||||
return pbm_regs + fire_imap_offset(ino);
|
||||
}
|
||||
|
||||
static unsigned int fire_irq_build(struct device_node *dp,
|
||||
unsigned int ino,
|
||||
void *_data)
|
||||
{
|
||||
struct fire_irq_data *irq_data = _data;
|
||||
unsigned long pbm_regs = irq_data->pbm_regs;
|
||||
unsigned long imap, iclr;
|
||||
unsigned long int_ctrlr;
|
||||
|
||||
ino &= 0x3f;
|
||||
|
||||
/* Now build the IRQ bucket. */
|
||||
imap = fire_ino_to_imap(pbm_regs, ino);
|
||||
iclr = fire_ino_to_iclr(pbm_regs, ino);
|
||||
|
||||
/* Set the interrupt controller number. */
|
||||
int_ctrlr = 1 << 6;
|
||||
upa_writeq(int_ctrlr, imap);
|
||||
|
||||
/* The interrupt map registers do not have an INO field
|
||||
* like other chips do. They return zero in the INO
|
||||
* field, and the interrupt controller number is controlled
|
||||
* in bits 6 thru 9. So in order for build_irq() to get
|
||||
* the INO right we pass it in as part of the fixup
|
||||
* which will get added to the map register zero value
|
||||
* read by build_irq().
|
||||
*/
|
||||
ino |= (irq_data->portid << 6);
|
||||
ino -= int_ctrlr;
|
||||
return build_irq(ino, iclr, imap);
|
||||
}
|
||||
|
||||
static void fire_irq_trans_init(struct device_node *dp)
|
||||
{
|
||||
const struct linux_prom64_registers *regs;
|
||||
struct fire_irq_data *irq_data;
|
||||
|
||||
dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
|
||||
dp->irq_trans->irq_build = fire_irq_build;
|
||||
|
||||
irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
|
||||
|
||||
regs = of_get_property(dp, "reg", NULL);
|
||||
dp->irq_trans->data = irq_data;
|
||||
|
||||
irq_data->pbm_regs = regs[0].phys_addr;
|
||||
irq_data->portid = of_getintprop_default(dp, "portid", 0);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_SBUS
|
||||
|
|
@ -1069,6 +1145,7 @@ static struct irq_trans pci_irq_trans_table[] = {
|
|||
{ "SUNW,tomatillo", tomatillo_irq_trans_init },
|
||||
{ "pci108e,a801", tomatillo_irq_trans_init },
|
||||
{ "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
|
||||
{ "pciex108e,80f0", fire_irq_trans_init },
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ struct iommu {
|
|||
unsigned long iommu_control;
|
||||
unsigned long iommu_tsbbase;
|
||||
unsigned long iommu_flush;
|
||||
unsigned long iommu_flushinv;
|
||||
unsigned long iommu_ctxflush;
|
||||
unsigned long write_complete_reg;
|
||||
unsigned long dummy_page;
|
||||
|
|
|
|||
Loading…
Reference in a new issue