V4L/DVB (7867): mxl5005s: Cleanup #4
Cleanup #4 Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Steven Toth
Mauro Carvalho Chehab
parent
3935c25484
commit
85d220d03b
2 changed files with 637 additions and 582 deletions
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@ -26,273 +26,48 @@
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#ifndef __MXL5005S_H
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#define __MXL5005S_H
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/*
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* The following context is source code provided by MaxLinear.
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* MaxLinear source code - Common.h
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*/
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/* IF frequency */
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enum IF_FREQ_HZ
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{
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IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz
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IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz
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IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz
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IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz
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IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz
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IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz
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IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz
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};
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typedef void *HANDLE; /* Pointer to memory location */
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/* Crystal frequency */
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enum CRYSTAL_FREQ_HZ
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{
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CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz
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CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz
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CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz
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CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz
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};
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#define TUNER_REGS_NUM 104
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#define INITCTRL_NUM 40
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struct mxl5005s_config
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{
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u8 i2c_address;
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#ifdef _MXL_PRODUCTION
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#define CHCTRL_NUM 39
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/* Stuff I don't know what to do with */
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u8 AgcMasterByte;
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};
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#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE))
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extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
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struct i2c_adapter *i2c,
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struct mxl5005s_config *config);
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#else
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#define CHCTRL_NUM 36
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#endif
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#define MXLCTRL_NUM 189
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#define MASTER_CONTROL_ADDR 9
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/* Enumeration of AGC Mode */
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typedef enum
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static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
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struct i2c_adapter *i2c,
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struct mxl5005s_config *config);
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{
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MXL_DUAL_AGC = 0,
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MXL_SINGLE_AGC
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} AGC_Mode;
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/* Enumeration of Master Control Register State */
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typedef enum
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{
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MC_LOAD_START = 1,
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MC_POWER_DOWN,
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MC_SYNTH_RESET,
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MC_SEQ_OFF
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} Master_Control_State;
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/* Enumeration of MXL5005 Tuner Mode */
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typedef enum
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{
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MXL_ANALOG_MODE = 0,
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MXL_DIGITAL_MODE
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} Tuner_Mode;
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/* Enumeration of MXL5005 Tuner IF Mode */
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typedef enum
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{
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MXL_ZERO_IF = 0,
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MXL_LOW_IF
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} Tuner_IF_Mode;
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/* Enumeration of MXL5005 Tuner Clock Out Mode */
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typedef enum
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{
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MXL_CLOCK_OUT_DISABLE = 0,
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MXL_CLOCK_OUT_ENABLE
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} Tuner_Clock_Out;
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/* Enumeration of MXL5005 Tuner Div Out Mode */
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typedef enum
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{
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MXL_DIV_OUT_1 = 0,
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MXL_DIV_OUT_4
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} Tuner_Div_Out;
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/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
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typedef enum
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{
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MXL_CAP_SEL_DISABLE = 0,
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MXL_CAP_SEL_ENABLE
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} Tuner_Cap_Select;
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/* Enumeration of MXL5005 Tuner RSSI Mode */
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typedef enum
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{
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MXL_RSSI_DISABLE = 0,
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MXL_RSSI_ENABLE
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} Tuner_RSSI;
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/* Enumeration of MXL5005 Tuner Modulation Type */
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typedef enum
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{
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MXL_DEFAULT_MODULATION = 0,
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MXL_DVBT,
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MXL_ATSC,
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MXL_QAM,
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MXL_ANALOG_CABLE,
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MXL_ANALOG_OTA
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} Tuner_Modu_Type;
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/* Enumeration of MXL5005 Tuner Tracking Filter Type */
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typedef enum
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{
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MXL_TF_DEFAULT = 0,
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MXL_TF_OFF,
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MXL_TF_C,
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MXL_TF_C_H,
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MXL_TF_D,
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MXL_TF_D_L,
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MXL_TF_E,
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MXL_TF_F,
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MXL_TF_E_2,
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MXL_TF_E_NA,
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MXL_TF_G
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} Tuner_TF_Type;
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/* MXL5005 Tuner Register Struct */
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typedef struct _TunerReg_struct
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{
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u16 Reg_Num; /* Tuner Register Address */
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u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
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} TunerReg_struct;
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typedef enum
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{
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/* Initialization Control Names */
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DN_IQTN_AMP_CUT = 1, /* 1 */
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BB_MODE, /* 2 */
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BB_BUF, /* 3 */
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BB_BUF_OA, /* 4 */
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BB_ALPF_BANDSELECT, /* 5 */
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BB_IQSWAP, /* 6 */
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BB_DLPF_BANDSEL, /* 7 */
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RFSYN_CHP_GAIN, /* 8 */
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RFSYN_EN_CHP_HIGAIN, /* 9 */
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AGC_IF, /* 10 */
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AGC_RF, /* 11 */
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IF_DIVVAL, /* 12 */
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IF_VCO_BIAS, /* 13 */
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CHCAL_INT_MOD_IF, /* 14 */
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CHCAL_FRAC_MOD_IF, /* 15 */
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DRV_RES_SEL, /* 16 */
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I_DRIVER, /* 17 */
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EN_AAF, /* 18 */
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EN_3P, /* 19 */
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EN_AUX_3P, /* 20 */
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SEL_AAF_BAND, /* 21 */
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SEQ_ENCLK16_CLK_OUT, /* 22 */
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SEQ_SEL4_16B, /* 23 */
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XTAL_CAPSELECT, /* 24 */
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IF_SEL_DBL, /* 25 */
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RFSYN_R_DIV, /* 26 */
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SEQ_EXTSYNTHCALIF, /* 27 */
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SEQ_EXTDCCAL, /* 28 */
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AGC_EN_RSSI, /* 29 */
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RFA_ENCLKRFAGC, /* 30 */
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RFA_RSSI_REFH, /* 31 */
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RFA_RSSI_REF, /* 32 */
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RFA_RSSI_REFL, /* 33 */
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RFA_FLR, /* 34 */
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RFA_CEIL, /* 35 */
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SEQ_EXTIQFSMPULSE, /* 36 */
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OVERRIDE_1, /* 37 */
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BB_INITSTATE_DLPF_TUNE, /* 38 */
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TG_R_DIV, /* 39 */
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EN_CHP_LIN_B, /* 40 */
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/* Channel Change Control Names */
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DN_POLY = 51, /* 51 */
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DN_RFGAIN, /* 52 */
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DN_CAP_RFLPF, /* 53 */
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DN_EN_VHFUHFBAR, /* 54 */
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DN_GAIN_ADJUST, /* 55 */
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DN_IQTNBUF_AMP, /* 56 */
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DN_IQTNGNBFBIAS_BST, /* 57 */
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RFSYN_EN_OUTMUX, /* 58 */
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RFSYN_SEL_VCO_OUT, /* 59 */
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RFSYN_SEL_VCO_HI, /* 60 */
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RFSYN_SEL_DIVM, /* 61 */
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RFSYN_RF_DIV_BIAS, /* 62 */
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DN_SEL_FREQ, /* 63 */
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RFSYN_VCO_BIAS, /* 64 */
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CHCAL_INT_MOD_RF, /* 65 */
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CHCAL_FRAC_MOD_RF, /* 66 */
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RFSYN_LPF_R, /* 67 */
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CHCAL_EN_INT_RF, /* 68 */
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TG_LO_DIVVAL, /* 69 */
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TG_LO_SELVAL, /* 70 */
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TG_DIV_VAL, /* 71 */
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TG_VCO_BIAS, /* 72 */
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SEQ_EXTPOWERUP, /* 73 */
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OVERRIDE_2, /* 74 */
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OVERRIDE_3, /* 75 */
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OVERRIDE_4, /* 76 */
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SEQ_FSM_PULSE, /* 77 */
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GPIO_4B, /* 78 */
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GPIO_3B, /* 79 */
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GPIO_4, /* 80 */
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GPIO_3, /* 81 */
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GPIO_1B, /* 82 */
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DAC_A_ENABLE, /* 83 */
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DAC_B_ENABLE, /* 84 */
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DAC_DIN_A, /* 85 */
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DAC_DIN_B, /* 86 */
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#ifdef _MXL_PRODUCTION
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RFSYN_EN_DIV, /* 87 */
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RFSYN_DIVM, /* 88 */
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DN_BYPASS_AGC_I2C /* 89 */
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#endif
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} MXL5005_ControlName;
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/* End of common.h */
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/*
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* The following context is source code provided by MaxLinear.
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* MaxLinear source code - Common_MXL.h (?)
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*/
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/* Constants */
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#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
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#define MXL5005S_LATCH_BYTE 0xfe
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/* Register address, MSB, and LSB */
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#define MXL5005S_BB_IQSWAP_ADDR 59
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#define MXL5005S_BB_IQSWAP_MSB 0
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#define MXL5005S_BB_IQSWAP_LSB 0
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#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
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#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
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#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
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/* Standard modes */
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enum
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{
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MXL5005S_STANDARD_DVBT,
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MXL5005S_STANDARD_ATSC,
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};
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#define MXL5005S_STANDARD_MODE_NUM 2
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/* Bandwidth modes */
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enum
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{
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MXL5005S_BANDWIDTH_6MHZ = 6000000,
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MXL5005S_BANDWIDTH_7MHZ = 7000000,
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MXL5005S_BANDWIDTH_8MHZ = 8000000,
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};
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#define MXL5005S_BANDWIDTH_MODE_NUM 3
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/* Top modes */
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enum
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{
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MXL5005S_TOP_5P5 = 55,
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MXL5005S_TOP_7P2 = 72,
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MXL5005S_TOP_9P2 = 92,
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MXL5005S_TOP_11P0 = 110,
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MXL5005S_TOP_12P9 = 129,
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MXL5005S_TOP_14P7 = 147,
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MXL5005S_TOP_16P8 = 168,
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MXL5005S_TOP_19P4 = 194,
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MXL5005S_TOP_21P2 = 212,
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MXL5005S_TOP_23P2 = 232,
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MXL5005S_TOP_25P2 = 252,
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MXL5005S_TOP_27P1 = 271,
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MXL5005S_TOP_29P2 = 292,
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MXL5005S_TOP_31P7 = 317,
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MXL5005S_TOP_34P9 = 349,
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};
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/* IF output load */
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enum
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{
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MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
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MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
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};
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/* End of common_mxl.h (?) */
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printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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#endif /* CONFIG_DVB_TUNER_MXL5005S */
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#endif /* __MXL5005S_H */
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