MIPS fixes for 4.17-rc2
Some MIPS fixes for 4.17: - io: Add barriers to read*() & write*() - dts: Fix boston PCI bus DTC warnings (4.17) - memset: Several corner case fixes (one 3.10, others longer) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAlrZ9EUACgkQbAtpk944 dnor8w/9EildyR3SOF4wGjfxQROnDnDzTdXSFEqldiVg7w6f9HmTtGLcHvP3i91t LqtSBslRk91qoj9/3Lop7Q4Ik5lnWOyhBzww4EienUr5DIHedV0G59aa7IzH8cZV Zke0s014z0wSZb1BcByKLc5ewpXVV1uaARxCp7jphh1WJZB4BaiISh35qn06v3Op xKQ1vNNDwyc/9Z/KxoR522ujmEiguzd/LTEfFmhA1Njy8gYbyciXWBEEeccQ9fOq kr0P2wg37+sqEvFkmKWnUO8bQq8M3J12hPzOuZRcvtqAcsFduRT1lIDrvbcKzRjD Eesuuh4p6+nFkpPnQw8rTfe5hnDN9f2l7FWSzMmOY02pwgG50uYIl2LDg9f4IG5o h89opjmHMYRHws+yeFsCkmDswMjauHuWI3ZyIa3xJ07OvZfO4LhRwq9oTn5B6iJl ymDV77Z73mXGy7MOZ56miT68+vTfAG3lxHe+Bnflr0IJ7xiDNqbkrvY8eMUQFAMY TCpv0MF3Se9TB9xqmQ2RuCVd1iGn/88m3AXcNlIDwAIcxAb2vikUDHS2rSEgQAo/ 7er9gZE8NnKo0qyQZustJDN+iLCyXoBbHpy8ZxJ89AYfDwLPyK3XmALjt7T7dZzn 326fXY4hy0EKuXsTX2YIHrzhWSBbR0tH8xx2aqu3AtrXY7K/Hcc= =TGOs -----END PGP SIGNATURE----- Merge tag 'mips_fixes_4.17_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS fixes from James Hogan: - io: Add barriers to read*() & write*() - dts: Fix boston PCI bus DTC warnings (4.17) - memset: Several corner case fixes (one 3.10, others longer) * tag 'mips_fixes_4.17_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: MIPS: uaccess: Add micromips clobbers to bzero invocation MIPS: memset.S: Fix clobber of v1 in last_fixup MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup MIPS: memset.S: EVA & fault support for small_memset MIPS: dts: Boston: Fix PCI bus dtc warnings: MIPS: io: Add barrier after register read in readX() MIPS: io: Prevent compiler reordering writeX()
This commit is contained in:
Linus Torvalds
commit
854da23875
4 changed files with 26 additions and 6 deletions
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@ -51,6 +51,8 @@
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ranges = <0x02000000 0 0x40000000
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0x40000000 0 0x40000000>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci0_intc 1>,
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<0 0 0 2 &pci0_intc 2>,
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@ -79,6 +81,8 @@
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ranges = <0x02000000 0 0x20000000
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0x20000000 0 0x20000000>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci1_intc 1>,
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<0 0 0 2 &pci1_intc 2>,
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@ -107,6 +111,8 @@
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ranges = <0x02000000 0 0x16000000
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0x16000000 0 0x100000>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci2_intc 1>,
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<0 0 0 2 &pci2_intc 2>,
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@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr)
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#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
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#define war_io_reorder_wmb() wmb()
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#else
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#define war_io_reorder_wmb() do { } while (0)
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#define war_io_reorder_wmb() barrier()
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#endif
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
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@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
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BUG(); \
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} \
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\
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/* prevent prefetching of coherent DMA data prematurely */ \
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rmb(); \
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return pfx##ioswab##bwlq(__mem, __val); \
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}
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@ -654,6 +654,13 @@ __clear_user(void __user *addr, __kernel_size_t size)
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{
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__kernel_size_t res;
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#ifdef CONFIG_CPU_MICROMIPS
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/* micromips memset / bzero also clobbers t7 & t8 */
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#define bzero_clobbers "$4", "$5", "$6", __UA_t0, __UA_t1, "$15", "$24", "$31"
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#else
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#define bzero_clobbers "$4", "$5", "$6", __UA_t0, __UA_t1, "$31"
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#endif /* CONFIG_CPU_MICROMIPS */
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if (eva_kernel_access()) {
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__asm__ __volatile__(
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"move\t$4, %1\n\t"
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@ -663,7 +670,7 @@ __clear_user(void __user *addr, __kernel_size_t size)
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"move\t%0, $6"
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: "=r" (res)
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: "r" (addr), "r" (size)
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: "$4", "$5", "$6", __UA_t0, __UA_t1, "$31");
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: bzero_clobbers);
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} else {
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might_fault();
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__asm__ __volatile__(
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@ -674,7 +681,7 @@ __clear_user(void __user *addr, __kernel_size_t size)
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"move\t%0, $6"
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: "=r" (res)
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: "r" (addr), "r" (size)
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: "$4", "$5", "$6", __UA_t0, __UA_t1, "$31");
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: bzero_clobbers);
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}
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return res;
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@ -219,7 +219,7 @@
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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bne t1, a0, 1b
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sb a1, -1(a0)
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EX(sb, a1, -1(a0), .Lsmall_fixup\@)
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2: jr ra /* done */
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move a2, zero
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@ -252,13 +252,18 @@
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PTR_L t0, TI_TASK($28)
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andi a2, STORMASK
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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LONG_ADDU a2, a0
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jr ra
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LONG_SUBU a2, t0
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.Llast_fixup\@:
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jr ra
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andi v1, a2, STORMASK
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nop
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.Lsmall_fixup\@:
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PTR_SUBU a2, t1, a0
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jr ra
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PTR_ADDIU a2, 1
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.endm
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