[ALSA] intel8x0 - Fix/cleanup detection of codecs on SIS7012
Modules: Intel8x0 driver Fix the detection of tertriary codec on SIS7012, including clean-ups of relevant codes. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
Jaroslav Kysela
parent
15f500a699
commit
84a43bd523
1 changed files with 84 additions and 54 deletions
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@ -178,6 +178,8 @@ DEFINE_REGSET(SP, 0x60); /* SPDIF out */
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#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
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#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
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#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
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#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
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#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
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#define ICH_MD3 0x00020000 /* modem power down semaphore */
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#define ICH_AD3 0x00010000 /* audio power down semaphore */
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#define ICH_RCS 0x00008000 /* read completion status */
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@ -398,6 +400,10 @@ struct intel8x0 {
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struct snd_ac97_bus *ac97_bus;
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struct snd_ac97 *ac97[3];
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unsigned int ac97_sdin[3];
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unsigned int max_codecs, ncodecs;
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unsigned int *codec_bit;
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unsigned int codec_isr_bits;
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unsigned int codec_ready_bits;
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spinlock_t reg_lock;
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@ -516,18 +522,6 @@ static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
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* access to AC97 codec via normal i/o (for ICH and SIS7012)
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*/
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/* return the GLOB_STA bit for the corresponding codec */
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static unsigned int get_ich_codec_bit(struct intel8x0 *chip, unsigned int codec)
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{
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static unsigned int codec_bit[3] = {
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ICH_PCR, ICH_SCR, ICH_TCR
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};
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snd_assert(codec < 3, return ICH_PCR);
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if (chip->device_type == DEVICE_INTEL_ICH4)
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codec = chip->ac97_sdin[codec];
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return codec_bit[codec];
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}
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static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
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{
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int time;
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@ -537,9 +531,9 @@ static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int code
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if (chip->in_sdin_init) {
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/* we don't know the ready bit assignment at the moment */
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/* so we check any */
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codec = ICH_PCR | ICH_SCR | ICH_TCR;
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codec = chip->codec_isr_bits;
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} else {
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codec = get_ich_codec_bit(chip, codec);
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codec = chip->codec_bit[chip->ac97_sdin[codec]];
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}
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/* codec ready ? */
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@ -596,7 +590,7 @@ static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
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if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
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/* reset RCS and preserve other R/WC bits */
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iputdword(chip, ICHREG(GLOB_STA), tmp &
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~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
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~(chip->codec_ready_bits | ICH_GSCI));
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if (! chip->in_ac97_init)
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snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
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res = 0xffff;
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@ -605,7 +599,8 @@ static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
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return res;
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}
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static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec)
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static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
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unsigned int codec)
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{
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unsigned int tmp;
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@ -614,7 +609,7 @@ static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int cod
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if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
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/* reset RCS and preserve other R/WC bits */
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iputdword(chip, ICHREG(GLOB_STA), tmp &
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~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
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~(chip->codec_ready_bits | ICH_GSCI));
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}
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}
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}
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@ -2078,23 +2073,24 @@ static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
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if (chip->device_type != DEVICE_ALI) {
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glob_sta = igetdword(chip, ICHREG(GLOB_STA));
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ops = &standard_bus_ops;
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if (chip->device_type == DEVICE_INTEL_ICH4) {
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codecs = 0;
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if (glob_sta & ICH_PCR)
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codecs++;
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if (glob_sta & ICH_SCR)
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codecs++;
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if (glob_sta & ICH_TCR)
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codecs++;
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chip->in_sdin_init = 1;
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for (i = 0; i < codecs; i++) {
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snd_intel8x0_codec_read_test(chip, i);
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chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
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}
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chip->in_sdin_init = 0;
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} else {
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codecs = glob_sta & ICH_SCR ? 2 : 1;
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chip->in_sdin_init = 1;
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codecs = 0;
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for (i = 0; i < chip->max_codecs; i++) {
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if (! (glob_sta & chip->codec_bit[i]))
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continue;
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if (chip->device_type == DEVICE_INTEL_ICH4) {
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snd_intel8x0_codec_read_test(chip, codecs);
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chip->ac97_sdin[codecs] =
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igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
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snd_assert(chip->ac97_sdin[codecs] < 3,
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chip->ac97_sdin[codecs] = 0);
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} else
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chip->ac97_sdin[codecs] = i;
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codecs++;
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}
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chip->in_sdin_init = 0;
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if (! codecs)
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codecs = 1;
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} else {
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ops = &ali_bus_ops;
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codecs = 1;
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@ -2120,6 +2116,7 @@ static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
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else
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pbus->dra = 1;
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chip->ac97_bus = pbus;
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chip->ncodecs = codecs;
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ac97.pci = chip->pci;
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for (i = 0; i < codecs; i++) {
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@ -2264,7 +2261,7 @@ static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
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end_time = jiffies + HZ;
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do {
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status = igetdword(chip, ICHREG(GLOB_STA)) &
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(ICH_PCR | ICH_SCR | ICH_TCR);
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chip->codec_isr_bits;
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if (status)
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break;
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schedule_timeout_uninterruptible(1);
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@ -2276,32 +2273,27 @@ static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
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return -EIO;
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}
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if (chip->device_type == DEVICE_INTEL_ICH4)
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/* ICH4 can have three codecs */
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nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
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else
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/* others up to two codecs */
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nstatus = ICH_PCR | ICH_SCR;
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/* wait for other codecs ready status. */
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end_time = jiffies + HZ / 4;
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while (status != nstatus && time_after_eq(end_time, jiffies)) {
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while (status != chip->codec_isr_bits &&
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time_after_eq(end_time, jiffies)) {
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schedule_timeout_uninterruptible(1);
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status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
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status |= igetdword(chip, ICHREG(GLOB_STA)) &
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chip->codec_isr_bits;
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}
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} else {
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/* resume phase */
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int i;
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status = 0;
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for (i = 0; i < 3; i++)
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for (i = 0; i < chip->ncodecs; i++)
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if (chip->ac97[i])
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status |= get_ich_codec_bit(chip, i);
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status |= chip->codec_bit[chip->ac97_sdin[i]];
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/* wait until all the probed codecs are ready */
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end_time = jiffies + HZ;
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do {
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nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
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(ICH_PCR | ICH_SCR | ICH_TCR);
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chip->codec_isr_bits;
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if (status == nstatus)
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break;
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schedule_timeout_uninterruptible(1);
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@ -2447,7 +2439,7 @@ static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
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}
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}
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}
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for (i = 0; i < 3; i++)
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for (i = 0; i < chip->ncodecs; i++)
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snd_ac97_suspend(chip->ac97[i]);
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if (chip->device_type == DEVICE_INTEL_ICH4)
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chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
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@ -2488,7 +2480,7 @@ static int intel8x0_resume(struct pci_dev *pci)
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if (chip->fix_nocache)
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fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
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for (i = 0; i < 3; i++)
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for (i = 0; i < chip->ncodecs; i++)
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snd_ac97_resume(chip->ac97[i]);
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/* refill nocache */
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@ -2619,12 +2611,20 @@ static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
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snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
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if (chip->device_type == DEVICE_INTEL_ICH4)
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snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
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snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
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tmp & ICH_PCR ? " primary" : "",
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tmp & ICH_SCR ? " secondary" : "",
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tmp & ICH_TCR ? " tertiary" : "",
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(tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
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if (chip->device_type == DEVICE_INTEL_ICH4)
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snd_iprintf(buffer, "AC'97 codecs ready :");
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if (tmp & chip->codec_isr_bits) {
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int i;
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static const char *codecs[3] = {
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"primary", "secondary", "tertiary"
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};
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for (i = 0; i < chip->max_codecs; i++)
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if (tmp & chip->codec_bit[i])
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snd_iprintf(buffer, " %s", codecs[i]);
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} else
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snd_iprintf(buffer, " none");
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snd_iprintf(buffer, "\n");
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if (chip->device_type == DEVICE_INTEL_ICH4 ||
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chip->device_type == DEVICE_SIS)
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snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
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chip->ac97_sdin[0],
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chip->ac97_sdin[1],
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@ -2653,6 +2653,13 @@ struct ich_reg_info {
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unsigned int offset;
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};
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static unsigned int ich_codec_bits[3] = {
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ICH_PCR, ICH_SCR, ICH_TCR
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};
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static unsigned int sis_codec_bits[3] = {
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ICH_PCR, ICH_SCR, ICH_SIS_TCR
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};
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static int __devinit snd_intel8x0_create(struct snd_card *card,
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struct pci_dev *pci,
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unsigned long device_type,
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@ -2835,6 +2842,29 @@ static int __devinit snd_intel8x0_create(struct snd_card *card,
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pci_set_master(pci);
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synchronize_irq(chip->irq);
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switch(chip->device_type) {
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case DEVICE_INTEL_ICH4:
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/* ICH4 can have three codecs */
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chip->max_codecs = 3;
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chip->codec_bit = ich_codec_bits;
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chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
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break;
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case DEVICE_SIS:
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/* recent SIS7012 can have three codecs */
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chip->max_codecs = 3;
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chip->codec_bit = sis_codec_bits;
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chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
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break;
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default:
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/* others up to two codecs */
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chip->max_codecs = 2;
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chip->codec_bit = ich_codec_bits;
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chip->codec_ready_bits = ICH_PRI | ICH_SRI;
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break;
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}
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for (i = 0; i < chip->max_codecs; i++)
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chip->codec_isr_bits |= chip->codec_bit[i];
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if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
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snd_intel8x0_free(chip);
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return err;
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