drivers/edac: Lindent e7xxx
Lindent cleanup of e7xxx_edac driver Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
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f4aff42653
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849a4c375a
1 changed files with 59 additions and 73 deletions
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@ -146,21 +146,17 @@ struct e7xxx_error_info {
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static const struct e7xxx_dev_info e7xxx_devs[] = {
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[E7500] = {
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.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
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.ctl_name = "E7500"
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},
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.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
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.ctl_name = "E7500"},
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[E7501] = {
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.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
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.ctl_name = "E7501"
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},
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.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
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.ctl_name = "E7501"},
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[E7505] = {
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.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
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.ctl_name = "E7505"
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},
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.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
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.ctl_name = "E7505"},
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[E7205] = {
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.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
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.ctl_name = "E7205"
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},
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.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
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.ctl_name = "E7205"},
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};
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/* FIXME - is this valid for both SECDED and S4ECD4ED? */
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@ -181,15 +177,15 @@ static inline int e7xxx_find_channel(u16 syndrome)
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}
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static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
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unsigned long page)
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unsigned long page)
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{
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u32 remap;
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struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
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struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
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debugf3("%s()\n", __func__);
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if ((page < pvt->tolm) ||
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((page >= 0x100000) && (page < pvt->remapbase)))
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((page >= 0x100000) && (page < pvt->remapbase)))
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return page;
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remap = (page - pvt->tolm) + pvt->remapbase;
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@ -201,8 +197,7 @@ static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
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return pvt->tolm - 1;
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}
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static void process_ce(struct mem_ctl_info *mci,
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struct e7xxx_error_info *info)
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static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
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{
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u32 error_1b, page;
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u16 syndrome;
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@ -213,7 +208,7 @@ static void process_ce(struct mem_ctl_info *mci,
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/* read the error address */
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error_1b = info->dram_celog_add;
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/* FIXME - should use PAGE_SHIFT */
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page = error_1b >> 6; /* convert the address to 4k page */
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page = error_1b >> 6; /* convert the address to 4k page */
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/* read the syndrome */
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syndrome = info->dram_celog_syndrome;
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/* FIXME - check for -1 */
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@ -229,8 +224,7 @@ static void process_ce_no_info(struct mem_ctl_info *mci)
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edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
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}
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static void process_ue(struct mem_ctl_info *mci,
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struct e7xxx_error_info *info)
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static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
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{
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u32 error_2b, block_page;
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int row;
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@ -239,7 +233,7 @@ static void process_ue(struct mem_ctl_info *mci,
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/* read the error address */
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error_2b = info->dram_uelog_add;
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/* FIXME - should use PAGE_SHIFT */
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block_page = error_2b >> 6; /* convert to 4k address */
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block_page = error_2b >> 6; /* convert to 4k address */
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row = edac_mc_find_csrow_by_page(mci, block_page);
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edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
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}
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@ -250,28 +244,26 @@ static void process_ue_no_info(struct mem_ctl_info *mci)
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edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
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}
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static void e7xxx_get_error_info (struct mem_ctl_info *mci,
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struct e7xxx_error_info *info)
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static void e7xxx_get_error_info(struct mem_ctl_info *mci,
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struct e7xxx_error_info *info)
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{
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struct e7xxx_pvt *pvt;
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pvt = (struct e7xxx_pvt *) mci->pvt_info;
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
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&info->dram_ferr);
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
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&info->dram_nerr);
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pvt = (struct e7xxx_pvt *)mci->pvt_info;
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
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if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
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pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
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&info->dram_celog_add);
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&info->dram_celog_add);
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pci_read_config_word(pvt->bridge_ck,
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E7XXX_DRAM_CELOG_SYNDROME,
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&info->dram_celog_syndrome);
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E7XXX_DRAM_CELOG_SYNDROME,
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&info->dram_celog_syndrome);
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}
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if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
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pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
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&info->dram_uelog_add);
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&info->dram_uelog_add);
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if (info->dram_ferr & 3)
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
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@ -280,8 +272,9 @@ static void e7xxx_get_error_info (struct mem_ctl_info *mci,
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
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}
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static int e7xxx_process_error_info (struct mem_ctl_info *mci,
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struct e7xxx_error_info *info, int handle_errors)
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static int e7xxx_process_error_info(struct mem_ctl_info *mci,
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struct e7xxx_error_info *info,
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int handle_errors)
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{
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int error_found;
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@ -342,7 +335,6 @@ static inline int dual_channel_active(u32 drc, int dev_idx)
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return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
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}
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/* Return DRB granularity (0=32mb, 1=64mb). */
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static inline int drb_granularity(u32 drc, int dev_idx)
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{
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@ -350,9 +342,8 @@ static inline int drb_granularity(u32 drc, int dev_idx)
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return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
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}
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static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
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int dev_idx, u32 drc)
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int dev_idx, u32 drc)
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{
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unsigned long last_cumul_size;
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int index;
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@ -422,13 +413,13 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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debugf0("%s(): mci\n", __func__);
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/* make sure error reporting method is sane */
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switch(edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_NMI:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_POLL;
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break;
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switch (edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_NMI:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_POLL;
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break;
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}
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pci_read_config_dword(pdev, E7XXX_DRC, &drc);
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@ -442,22 +433,21 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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debugf3("%s(): init mci\n", __func__);
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mci->mtype_cap = MEM_FLAG_RDDR;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
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EDAC_FLAG_S4ECD4ED;
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EDAC_FLAG_S4ECD4ED;
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/* FIXME - what if different memory types are in different csrows? */
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = E7XXX_REVISION;
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mci->dev = &pdev->dev;
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debugf3("%s(): init pvt\n", __func__);
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pvt = (struct e7xxx_pvt *) mci->pvt_info;
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pvt = (struct e7xxx_pvt *)mci->pvt_info;
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pvt->dev_info = &e7xxx_devs[dev_idx];
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pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
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pvt->dev_info->err_dev,
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pvt->bridge_ck);
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pvt->dev_info->err_dev, pvt->bridge_ck);
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if (!pvt->bridge_ck) {
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e7xxx_printk(KERN_ERR, "error reporting device not found:"
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
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goto fail0;
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}
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@ -477,8 +467,8 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
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pvt->remaplimit = ((u32) pci_data) << 14;
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e7xxx_printk(KERN_INFO,
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"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
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pvt->remapbase, pvt->remaplimit);
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"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
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pvt->remapbase, pvt->remaplimit);
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/* clear any pending errors, or initial state bits */
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e7xxx_get_error_info(mci, &discard);
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/* Here we assume that we will never see multiple instances of this
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* type of memory controller. The ID is therefore hardcoded to 0.
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*/
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if (edac_mc_add_mc(mci,0)) {
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if (edac_mc_add_mc(mci, 0)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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goto fail1;
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}
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@ -495,10 +485,10 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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debugf3("%s(): success\n", __func__);
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return 0;
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fail1:
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fail1:
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pci_dev_put(pvt->bridge_ck);
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fail0:
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fail0:
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edac_mc_free(mci);
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return -ENODEV;
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/* returns count (>= 0), or negative on error */
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static int __devinit e7xxx_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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const struct pci_device_id *ent)
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{
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debugf0("%s()\n", __func__);
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/* wake up and enable device */
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return pci_enable_device(pdev) ?
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-EIO : e7xxx_probe1(pdev, ent->driver_data);
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-EIO : e7xxx_probe1(pdev, ent->driver_data);
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}
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static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
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@ -525,31 +515,27 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
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return;
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pvt = (struct e7xxx_pvt *) mci->pvt_info;
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pvt = (struct e7xxx_pvt *)mci->pvt_info;
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pci_dev_put(pvt->bridge_ck);
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edac_mc_free(mci);
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}
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static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
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{
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PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7205
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},
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PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7205},
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{
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PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7500
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},
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PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7500},
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{
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PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7501
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},
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PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7501},
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{
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PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7505
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},
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PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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E7505},
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{
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0,
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} /* 0 terminated list. */
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0,
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} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
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@ -576,7 +562,7 @@ module_exit(e7xxx_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
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"Based on.work by Dan Hollis et al");
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"Based on.work by Dan Hollis et al");
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MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
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module_param(edac_op_state, int, 0444);
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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