[ALSA] cs4270: wrong sample rate when CONFIG_SND_SOC_CS4270_VD33_ERRATA is set
When CONFIG_SND_SOC_CS4270_VD33_ERRATA is set, there was a mismatch between the mclk_ratios[] and cs4270_mode_ratios[] arrays. The two arrays have been merged and code has been shuffled. One side effect is that the cs4270_set_dai_sysclk() and cs4270_set_dai_fmt() functions are available only if I2C has been enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Timur Tabi
Jaroslav Kysela
parent
b7d2a8035a
commit
8432395fd9
1 changed files with 154 additions and 159 deletions
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@ -48,112 +48,6 @@ struct cs4270_private {
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unsigned int mode; /* The mode (I2S or left-justified) */
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};
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/* The number of MCLK/LRCK ratios supported by the CS4270 */
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#define NUM_MCLK_RATIOS 9
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/* The actual MCLK/LRCK ratios, in increasing numerical order */
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static unsigned int mclk_ratios[NUM_MCLK_RATIOS] =
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{64, 96, 128, 192, 256, 384, 512, 768, 1024};
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/*
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* Determine the CS4270 samples rates.
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*
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* 'freq' is the input frequency to MCLK. The other parameters are ignored.
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*
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* The value of MCLK is used to determine which sample rates are supported
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* by the CS4270. The ratio of MCLK / Fs must be equal to one of nine
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* support values: 64, 96, 128, 192, 256, 384, 512, 768, and 1024.
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*
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* This function calculates the nine ratios and determines which ones match
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* a standard sample rate. If there's a match, then it is added to the list
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* of support sample rates.
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*
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* This function must be called by the machine driver's 'startup' function,
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* otherwise the list of supported sample rates will not be available in
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* time for ALSA.
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*
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* Note that in stand-alone mode, the sample rate is determined by input
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* pins M0, M1, MDIV1, and MDIV2. Also in stand-alone mode, divide-by-3
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* is not a programmable option. However, divide-by-3 is not an available
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* option in stand-alone mode. This cases two problems: a ratio of 768 is
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* not available (it requires divide-by-3) and B) ratios 192 and 384 can
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* only be selected with divide-by-1.5, but there is an errate that make
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* this selection difficult.
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*
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* In addition, there is no mechanism for communicating with the machine
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* driver what the input settings can be. This would need to be implemented
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* for stand-alone mode to work.
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*/
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static int cs4270_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct cs4270_private *cs4270 = codec->private_data;
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unsigned int rates = 0;
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unsigned int rate_min = -1;
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unsigned int rate_max = 0;
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unsigned int i;
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cs4270->mclk = freq;
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for (i = 0; i < NUM_MCLK_RATIOS; i++) {
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unsigned int rate = freq / mclk_ratios[i];
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rates |= snd_pcm_rate_to_rate_bit(rate);
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if (rate < rate_min)
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rate_min = rate;
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if (rate > rate_max)
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rate_max = rate;
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}
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/* FIXME: soc should support a rate list */
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rates &= ~SNDRV_PCM_RATE_KNOT;
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if (!rates) {
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printk(KERN_ERR "cs4270: could not find a valid sample rate\n");
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return -EINVAL;
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}
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codec_dai->playback.rates = rates;
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codec_dai->playback.rate_min = rate_min;
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codec_dai->playback.rate_max = rate_max;
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codec_dai->capture.rates = rates;
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codec_dai->capture.rate_min = rate_min;
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codec_dai->capture.rate_max = rate_max;
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return 0;
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}
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/*
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* Configure the codec for the selected audio format
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*
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* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
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* codec accordingly.
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*
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* Currently, this function only supports SND_SOC_DAIFMT_I2S and
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* SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified
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* data for playback only, but ASoC currently does not support different
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* formats for playback vs. record.
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*/
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static int cs4270_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
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unsigned int format)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct cs4270_private *cs4270 = codec->private_data;
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int ret = 0;
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switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
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break;
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default:
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printk(KERN_ERR "cs4270: invalid DAI format\n");
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ret = -EINVAL;
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}
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return ret;
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}
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/*
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* The codec isn't really big-endian or little-endian, since the I2S
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* interface requires data to be sent serially with the MSbit first.
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@ -228,6 +122,156 @@ static int cs4270_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
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#define CS4270_MUTE_DAC_A 0x01
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#define CS4270_MUTE_DAC_B 0x02
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/*
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* Clock Ratio Selection for Master Mode with I2C enabled
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*
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* The data for this chart is taken from Table 5 of the CS4270 reference
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* manual.
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*
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* This table is used to determine how to program the Mode Control register.
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* It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling
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* rates the CS4270 currently supports.
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*
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* Each element in this array corresponds to the ratios in mclk_ratios[].
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* These two arrays need to be in sync.
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*
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* 'speed_mode' is the corresponding bit pattern to be written to the
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* MODE bits of the Mode Control Register
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*
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* 'mclk' is the corresponding bit pattern to be wirten to the MCLK bits of
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* the Mode Control Register.
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*
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* In situations where a single ratio is represented by multiple speed
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* modes, we favor the slowest speed. E.g, for a ratio of 128, we pick
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* double-speed instead of quad-speed. However, the CS4270 errata states
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* that Divide-By-1.5 can cause failures, so we avoid that mode where
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* possible.
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*
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* ERRATA: There is an errata for the CS4270 where divide-by-1.5 does not
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* work if VD = 3.3V. If this effects you, select the
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* CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will
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* never select any sample rates that require divide-by-1.5.
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*/
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static struct {
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unsigned int ratio;
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u8 speed_mode;
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u8 mclk;
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} cs4270_mode_ratios[] = {
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{64, CS4270_MODE_4X, CS4270_MODE_DIV1},
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#ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA
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{96, CS4270_MODE_4X, CS4270_MODE_DIV15},
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#endif
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{128, CS4270_MODE_2X, CS4270_MODE_DIV1},
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{192, CS4270_MODE_4X, CS4270_MODE_DIV3},
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{256, CS4270_MODE_1X, CS4270_MODE_DIV1},
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{384, CS4270_MODE_2X, CS4270_MODE_DIV3},
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{512, CS4270_MODE_1X, CS4270_MODE_DIV2},
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{768, CS4270_MODE_1X, CS4270_MODE_DIV3},
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{1024, CS4270_MODE_1X, CS4270_MODE_DIV4}
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};
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/* The number of MCLK/LRCK ratios supported by the CS4270 */
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#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios)
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/*
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* Determine the CS4270 samples rates.
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*
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* 'freq' is the input frequency to MCLK. The other parameters are ignored.
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*
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* The value of MCLK is used to determine which sample rates are supported
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* by the CS4270. The ratio of MCLK / Fs must be equal to one of nine
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* support values: 64, 96, 128, 192, 256, 384, 512, 768, and 1024.
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*
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* This function calculates the nine ratios and determines which ones match
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* a standard sample rate. If there's a match, then it is added to the list
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* of support sample rates.
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*
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* This function must be called by the machine driver's 'startup' function,
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* otherwise the list of supported sample rates will not be available in
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* time for ALSA.
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*
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* Note that in stand-alone mode, the sample rate is determined by input
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* pins M0, M1, MDIV1, and MDIV2. Also in stand-alone mode, divide-by-3
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* is not a programmable option. However, divide-by-3 is not an available
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* option in stand-alone mode. This cases two problems: a ratio of 768 is
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* not available (it requires divide-by-3) and B) ratios 192 and 384 can
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* only be selected with divide-by-1.5, but there is an errate that make
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* this selection difficult.
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*
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* In addition, there is no mechanism for communicating with the machine
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* driver what the input settings can be. This would need to be implemented
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* for stand-alone mode to work.
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*/
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static int cs4270_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct cs4270_private *cs4270 = codec->private_data;
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unsigned int rates = 0;
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unsigned int rate_min = -1;
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unsigned int rate_max = 0;
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unsigned int i;
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cs4270->mclk = freq;
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for (i = 0; i < NUM_MCLK_RATIOS; i++) {
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unsigned int rate = freq / cs4270_mode_ratios[i].ratio;
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rates |= snd_pcm_rate_to_rate_bit(rate);
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if (rate < rate_min)
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rate_min = rate;
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if (rate > rate_max)
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rate_max = rate;
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}
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/* FIXME: soc should support a rate list */
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rates &= ~SNDRV_PCM_RATE_KNOT;
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if (!rates) {
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printk(KERN_ERR "cs4270: could not find a valid sample rate\n");
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return -EINVAL;
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}
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codec_dai->playback.rates = rates;
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codec_dai->playback.rate_min = rate_min;
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codec_dai->playback.rate_max = rate_max;
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codec_dai->capture.rates = rates;
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codec_dai->capture.rate_min = rate_min;
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codec_dai->capture.rate_max = rate_max;
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return 0;
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}
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/*
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* Configure the codec for the selected audio format
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*
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* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
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* codec accordingly.
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*
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* Currently, this function only supports SND_SOC_DAIFMT_I2S and
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* SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified
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* data for playback only, but ASoC currently does not support different
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* formats for playback vs. record.
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*/
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static int cs4270_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
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unsigned int format)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct cs4270_private *cs4270 = codec->private_data;
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int ret = 0;
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switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
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break;
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default:
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printk(KERN_ERR "cs4270: invalid DAI format\n");
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ret = -EINVAL;
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}
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return ret;
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}
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/*
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* A list of addresses on which this CS4270 could use. I2C addresses are
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* 7 bits. For the CS4270, the upper four bits are always 1001, and the
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@ -314,53 +358,6 @@ static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg,
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return 0;
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}
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/*
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* Clock Ratio Selection for Master Mode with I2C enabled
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*
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* The data for this chart is taken from Table 5 of the CS4270 reference
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* manual.
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*
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* This table is used to determine how to program the Mode Control register.
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* It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling
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* rates the CS4270 currently supports.
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*
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* Each element in this array corresponds to the ratios in mclk_ratios[].
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* These two arrays need to be in sync.
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*
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* 'speed_mode' is the corresponding bit pattern to be written to the
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* MODE bits of the Mode Control Register
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*
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* 'mclk' is the corresponding bit pattern to be wirten to the MCLK bits of
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* the Mode Control Register.
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*
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* In situations where a single ratio is represented by multiple speed
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* modes, we favor the slowest speed. E.g, for a ratio of 128, we pick
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* double-speed instead of quad-speed. However, the CS4270 errata states
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* that Divide-By-1.5 can cause failures, so we avoid that mode where
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* possible.
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*
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* ERRATA: There is an errata for the CS4270 where divide-by-1.5 does not
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* work if VD = 3.3V. If this effects you, select the
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* CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will
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* never select any sample rates that require divide-by-1.5.
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*/
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static struct {
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u8 speed_mode;
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u8 mclk;
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} cs4270_mode_ratios[NUM_MCLK_RATIOS] = {
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{CS4270_MODE_4X, CS4270_MODE_DIV1}, /* 64 */
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#ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA
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{CS4270_MODE_4X, CS4270_MODE_DIV15}, /* 96 */
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#endif
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{CS4270_MODE_2X, CS4270_MODE_DIV1}, /* 128 */
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{CS4270_MODE_4X, CS4270_MODE_DIV3}, /* 192 */
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{CS4270_MODE_1X, CS4270_MODE_DIV1}, /* 256 */
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{CS4270_MODE_2X, CS4270_MODE_DIV3}, /* 384 */
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{CS4270_MODE_1X, CS4270_MODE_DIV2}, /* 512 */
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{CS4270_MODE_1X, CS4270_MODE_DIV3}, /* 768 */
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{CS4270_MODE_1X, CS4270_MODE_DIV4} /* 1024 */
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};
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/*
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* Program the CS4270 with the given hardware parameters.
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*
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@ -388,7 +385,7 @@ static int cs4270_hw_params(struct snd_pcm_substream *substream,
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ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */
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for (i = 0; i < NUM_MCLK_RATIOS; i++) {
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if (mclk_ratios[i] == ratio)
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if (cs4270_mode_ratios[i].ratio == ratio)
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break;
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}
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@ -669,7 +666,7 @@ static int cs4270_i2c_probe(struct i2c_adapter *adapter, int addr, int kind)
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return ret;
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}
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#endif
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#endif /* USE_I2C*/
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struct snd_soc_codec_dai cs4270_dai = {
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.name = "CS4270",
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@ -687,10 +684,6 @@ struct snd_soc_codec_dai cs4270_dai = {
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.rates = 0,
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.formats = CS4270_FORMATS,
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},
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.dai_ops = {
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.set_sysclk = cs4270_set_dai_sysclk,
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.set_fmt = cs4270_set_dai_fmt,
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}
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};
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EXPORT_SYMBOL_GPL(cs4270_dai);
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@ -752,6 +745,8 @@ static int cs4270_probe(struct platform_device *pdev)
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if (codec->control_data) {
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/* Initialize codec ops */
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cs4270_dai.ops.hw_params = cs4270_hw_params;
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cs4270_dai.dai_ops.set_sysclk = cs4270_set_dai_sysclk;
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cs4270_dai.dai_ops.set_fmt = cs4270_set_dai_fmt;
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#ifdef CONFIG_SND_SOC_CS4270_HWMUTE
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cs4270_dai.dai_ops.digital_mute = cs4270_mute;
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#endif
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