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clk: mvebu: Fix ratio register offset on A375 SoC

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This commit fixes the ratio register offset which is 0x4,
as per the Armada 375 SoC specification.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Ezequiel Garcia 2014-03-12 12:41:41 -03:00 committed by Jason Cooper
parent e9646fe116
commit 8230a5ab43
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/mvebu/clk-corediv.c
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@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
.set_rate = clk_corediv_set_rate,
},
.ratio_reload = BIT(8),
.ratio_offset = 0x8,
.ratio_offset = 0x4,
};
static void __init