ASoC: OMAP: mcbsp.h: Clean up bit definitions
Use BIT() for bit position, correct field definition by adding mask to them, and also adding the missing spaces around '<<' Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Liam Girdwood <lrg@ti.com>
This commit is contained in:
Peter Ujfalusi
Liam Girdwood
parent
20456242e8
commit
81da6a9e49
1 changed files with 97 additions and 97 deletions
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@ -89,130 +89,130 @@ enum {
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#define OMAP_ST_REG_SSELCR 0x2C
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/************************** McBSP SPCR1 bit definitions ***********************/
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#define RRST 0x0001
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#define RRDY 0x0002
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#define RFULL 0x0004
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#define RSYNC_ERR 0x0008
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#define RINTM(value) ((value)<<4) /* bits 4:5 */
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#define ABIS 0x0040
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#define DXENA 0x0080
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#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
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#define RJUST(value) ((value)<<13) /* bits 13:14 */
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#define ALB 0x8000
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#define DLB 0x8000
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#define RRST BIT(0)
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#define RRDY BIT(1)
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#define RFULL BIT(2)
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#define RSYNC_ERR BIT(3)
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#define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
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#define ABIS BIT(6)
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#define DXENA BIT(7)
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#define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */
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#define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */
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#define ALB BIT(15)
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#define DLB BIT(15)
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/************************** McBSP SPCR2 bit definitions ***********************/
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#define XRST 0x0001
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#define XRDY 0x0002
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#define XEMPTY 0x0004
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#define XSYNC_ERR 0x0008
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#define XINTM(value) ((value)<<4) /* bits 4:5 */
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#define GRST 0x0040
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#define FRST 0x0080
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#define SOFT 0x0100
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#define FREE 0x0200
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#define XRST BIT(0)
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#define XRDY BIT(1)
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#define XEMPTY BIT(2)
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#define XSYNC_ERR BIT(3)
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#define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
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#define GRST BIT(6)
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#define FRST BIT(7)
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#define SOFT BIT(8)
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#define FREE BIT(9)
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/************************** McBSP PCR bit definitions *************************/
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#define CLKRP 0x0001
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#define CLKXP 0x0002
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#define FSRP 0x0004
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#define FSXP 0x0008
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#define DR_STAT 0x0010
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#define DX_STAT 0x0020
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#define CLKS_STAT 0x0040
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#define SCLKME 0x0080
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#define CLKRM 0x0100
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#define CLKXM 0x0200
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#define FSRM 0x0400
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#define FSXM 0x0800
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#define RIOEN 0x1000
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#define XIOEN 0x2000
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#define IDLE_EN 0x4000
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#define CLKRP BIT(0)
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#define CLKXP BIT(1)
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#define FSRP BIT(2)
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#define FSXP BIT(3)
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#define DR_STAT BIT(4)
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#define DX_STAT BIT(5)
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#define CLKS_STAT BIT(6)
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#define SCLKME BIT(7)
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#define CLKRM BIT(8)
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#define CLKXM BIT(9)
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#define FSRM BIT(10)
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#define FSXM BIT(11)
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#define RIOEN BIT(12)
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#define XIOEN BIT(13)
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#define IDLE_EN BIT(14)
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/************************** McBSP RCR1 bit definitions ************************/
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#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
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#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
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#define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
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#define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
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/************************** McBSP XCR1 bit definitions ************************/
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#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
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#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
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#define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
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#define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
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/*************************** McBSP RCR2 bit definitions ***********************/
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#define RDATDLY(value) (value) /* Bits 0:1 */
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#define RFIG 0x0004
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#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
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#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
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#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
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#define RPHASE 0x8000
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#define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
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#define RFIG BIT(2)
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#define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
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#define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
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#define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
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#define RPHASE BIT(15)
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/*************************** McBSP XCR2 bit definitions ***********************/
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#define XDATDLY(value) (value) /* Bits 0:1 */
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#define XFIG 0x0004
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#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
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#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
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#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
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#define XPHASE 0x8000
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#define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
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#define XFIG BIT(2)
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#define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
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#define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
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#define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
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#define XPHASE BIT(15)
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/************************* McBSP SRGR1 bit definitions ************************/
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#define CLKGDV(value) (value) /* Bits 0:7 */
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#define FWID(value) ((value)<<8) /* Bits 8:15 */
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#define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */
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#define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */
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/************************* McBSP SRGR2 bit definitions ************************/
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#define FPER(value) (value) /* Bits 0:11 */
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#define FSGM 0x1000
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#define CLKSM 0x2000
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#define CLKSP 0x4000
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#define GSYNC 0x8000
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#define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */
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#define FSGM BIT(12)
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#define CLKSM BIT(13)
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#define CLKSP BIT(14)
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#define GSYNC BIT(15)
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/************************* McBSP MCR1 bit definitions *************************/
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#define RMCM 0x0001
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#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
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#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
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#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
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#define RMCM BIT(0)
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#define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
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#define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
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#define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
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/************************* McBSP MCR2 bit definitions *************************/
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#define XMCM(value) (value) /* Bits 0:1 */
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#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
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#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
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#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
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#define XMCM(value) ((value) & 0x3) /* Bits 0:1 */
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#define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
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#define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
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#define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
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/*********************** McBSP XCCR bit definitions *************************/
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#define EXTCLKGATE 0x8000
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#define PPCONNECT 0x4000
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#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
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#define XFULL_CYCLE 0x0800
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#define DILB 0x0020
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#define XDMAEN 0x0008
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#define XDISABLE 0x0001
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#define XDISABLE BIT(0)
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#define XDMAEN BIT(3)
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#define DILB BIT(5)
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#define XFULL_CYCLE BIT(11)
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#define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */
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#define PPCONNECT BIT(14)
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#define EXTCLKGATE BIT(15)
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/********************** McBSP RCCR bit definitions *************************/
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#define RFULL_CYCLE 0x0800
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#define RDMAEN 0x0008
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#define RDISABLE 0x0001
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#define RDISABLE BIT(0)
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#define RDMAEN BIT(3)
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#define RFULL_CYCLE BIT(11)
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/********************** McBSP SYSCONFIG bit definitions ********************/
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#define CLOCKACTIVITY(value) ((value)<<8)
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#define SIDLEMODE(value) ((value)<<3)
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#define ENAWAKEUP 0x0004
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#define SOFTRST 0x0002
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#define SOFTRST BIT(1)
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#define ENAWAKEUP BIT(2)
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#define SIDLEMODE(value) (((value) & 0x3) << 3)
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#define CLOCKACTIVITY(value) (((value) & 0x3) << 8)
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/********************** McBSP SSELCR bit definitions ***********************/
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#define SIDETONEEN 0x0400
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#define SIDETONEEN BIT(10)
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/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
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#define ST_AUTOIDLE 0x0001
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#define ST_AUTOIDLE BIT(0)
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/********************** McBSP Sidetone SGAINCR bit definitions *************/
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#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
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#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
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#define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */
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#define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */
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/********************** McBSP Sidetone SFIRCR bit definitions **************/
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#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
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#define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */
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/********************** McBSP Sidetone SSELCR bit definitions **************/
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#define ST_COEFFWRDONE 0x0004
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#define ST_COEFFWREN 0x0002
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#define ST_SIDETONEEN 0x0001
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#define ST_SIDETONEEN BIT(0)
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#define ST_COEFFWREN BIT(1)
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#define ST_COEFFWRDONE BIT(2)
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/********************** McBSP DMA operating modes **************************/
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#define MCBSP_DMA_MODE_ELEMENT 0
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@ -220,15 +220,15 @@ enum {
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#define MCBSP_DMA_MODE_FRAME 2
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/********************** McBSP WAKEUPEN bit definitions *********************/
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#define XEMPTYEOFEN 0x4000
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#define XRDYEN 0x0400
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#define XEOFEN 0x0200
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#define XFSXEN 0x0100
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#define XSYNCERREN 0x0080
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#define RRDYEN 0x0008
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#define REOFEN 0x0004
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#define RFSREN 0x0002
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#define RSYNCERREN 0x0001
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#define RSYNCERREN BIT(0)
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#define RFSREN BIT(1)
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#define REOFEN BIT(2)
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#define RRDYEN BIT(3)
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#define XSYNCERREN BIT(7)
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#define XFSXEN BIT(8)
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#define XEOFEN BIT(9)
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#define XRDYEN BIT(10)
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#define XEMPTYEOFEN BIT(14)
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/* we don't do multichannel for now */
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struct omap_mcbsp_reg_cfg {
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