powerpc/mm: extend _PAGE_PRIVILEGED to all CPUs
commit ac29c64089
("powerpc/mm: Replace _PAGE_USER with
_PAGE_PRIVILEGED") introduced _PAGE_PRIVILEGED for BOOK3S/64
This patch generalises _PAGE_PRIVILEGED for all CPUs, allowing
to have either _PAGE_PRIVILEGED or _PAGE_USER or both.
PPC_8xx has a _PAGE_SHARED flag which is set for and only for
all non user pages. Lets rename it _PAGE_PRIVILEGED to remove
confusion as it has nothing to do with Linux shared pages.
On BookE, there's a _PAGE_BAP_SR which has to be set for kernel
pages: defining _PAGE_PRIVILEGED as _PAGE_BAP_SR will make
this generic
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
parent
5f356497c3
commit
812fadcb94
10 changed files with 28 additions and 54 deletions
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@ -15,7 +15,7 @@
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#define _PAGE_BIT_SWAP_TYPE 0
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#define _PAGE_BIT_SWAP_TYPE 0
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#define _PAGE_RO 0
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#define _PAGE_RO 0
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#define _PAGE_SHARED 0
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#define _PAGE_USER 0
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#define _PAGE_EXEC 0x00001 /* execute permission */
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#define _PAGE_EXEC 0x00001 /* execute permission */
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#define _PAGE_WRITE 0x00002 /* write access allowed */
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#define _PAGE_WRITE 0x00002 /* write access allowed */
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@ -31,7 +31,7 @@
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/* Definitions for 8xx embedded chips. */
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/* Definitions for 8xx embedded chips. */
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#define _PAGE_PRESENT 0x0001 /* Page is valid */
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#define _PAGE_PRESENT 0x0001 /* Page is valid */
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#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
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#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
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#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
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#define _PAGE_PRIVILEGED 0x0004 /* No ASID (context) compare */
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#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
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#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
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#define _PAGE_DIRTY 0x0100 /* C: page changed */
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#define _PAGE_DIRTY 0x0100 /* C: page changed */
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@ -54,13 +54,5 @@
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/* Until my rework is finished, 8xx still needs atomic PTE updates */
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/* Until my rework is finished, 8xx still needs atomic PTE updates */
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#define PTE_ATOMIC_UPDATES 1
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#define PTE_ATOMIC_UPDATES 1
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/* We need to add _PAGE_SHARED to kernel pages */
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#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_RO)
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#define _PAGE_KERNEL_ROX (_PAGE_SHARED | _PAGE_RO | _PAGE_EXEC)
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#define _PAGE_KERNEL_RW (_PAGE_SHARED | _PAGE_DIRTY | _PAGE_RW | \
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_PAGE_HWWRITE)
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#define _PAGE_KERNEL_RWX (_PAGE_SHARED | _PAGE_DIRTY | _PAGE_RW | \
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_PAGE_HWWRITE | _PAGE_EXEC)
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#endif /* __KERNEL__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
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@ -55,6 +55,7 @@
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_PRIVILEGED (_PAGE_BAP_SR)
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#define _PAGE_HASHPTE 0
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#define _PAGE_HASHPTE 0
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#define _PAGE_BUSY 0
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#define _PAGE_BUSY 0
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@ -8,9 +8,6 @@
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#ifndef _PAGE_HASHPTE
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#ifndef _PAGE_HASHPTE
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#define _PAGE_HASHPTE 0
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#define _PAGE_HASHPTE 0
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#endif
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#endif
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#ifndef _PAGE_SHARED
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#define _PAGE_SHARED 0
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#endif
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#ifndef _PAGE_HWWRITE
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#ifndef _PAGE_HWWRITE
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#define _PAGE_HWWRITE 0
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#define _PAGE_HWWRITE 0
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#endif
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#endif
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@ -45,6 +42,14 @@
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#ifndef _PAGE_PTE
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#ifndef _PAGE_PTE
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#define _PAGE_PTE 0
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#define _PAGE_PTE 0
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#endif
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#endif
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/* At least one of _PAGE_PRIVILEGED or _PAGE_USER must be defined */
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#ifndef _PAGE_PRIVILEGED
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#define _PAGE_PRIVILEGED 0
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#else
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#ifndef _PAGE_USER
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#define _PAGE_USER 0
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#endif
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#endif
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#ifndef _PMD_PRESENT_MASK
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#ifndef _PMD_PRESENT_MASK
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#define _PMD_PRESENT_MASK _PMD_PRESENT
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#define _PMD_PRESENT_MASK _PMD_PRESENT
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@ -54,16 +59,18 @@
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#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
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#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
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#endif
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#endif
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#ifndef _PAGE_KERNEL_RO
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#ifndef _PAGE_KERNEL_RO
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#define _PAGE_KERNEL_RO (_PAGE_RO)
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#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_RO)
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#endif
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#endif
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#ifndef _PAGE_KERNEL_ROX
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#ifndef _PAGE_KERNEL_ROX
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#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_RO)
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#define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_RO | _PAGE_EXEC)
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#endif
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#endif
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#ifndef _PAGE_KERNEL_RW
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#ifndef _PAGE_KERNEL_RW
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
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#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | \
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_PAGE_HWWRITE)
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#endif
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#endif
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#ifndef _PAGE_KERNEL_RWX
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#ifndef _PAGE_KERNEL_RWX
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE | _PAGE_EXEC)
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#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | \
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_PAGE_HWWRITE | _PAGE_EXEC)
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#endif
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#endif
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#ifndef _PAGE_HPTEFLAGS
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#ifndef _PAGE_HPTEFLAGS
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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@ -85,7 +92,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
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*/
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*/
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static inline bool pte_user(pte_t pte)
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static inline bool pte_user(pte_t pte)
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{
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{
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return (pte_val(pte) & _PAGE_USER) == _PAGE_USER;
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return (pte_val(pte) & (_PAGE_USER | _PAGE_PRIVILEGED)) == _PAGE_USER;
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}
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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@ -116,6 +123,7 @@ static inline bool pte_user(pte_t pte)
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#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
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#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU | _PAGE_ENDIAN | _PAGE_4K_PFN | \
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_PAGE_WRITETHRU | _PAGE_ENDIAN | _PAGE_4K_PFN | \
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_PAGE_USER | _PAGE_ACCESSED | _PAGE_RO | \
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_PAGE_USER | _PAGE_ACCESSED | _PAGE_RO | \
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_PAGE_PRIVILEGED | \
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_PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
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_PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
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/*
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/*
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@ -678,7 +678,7 @@ DTLBMissIMMR:
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mtspr SPRN_MD_TWC, r10
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mtspr SPRN_MD_TWC, r10
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mfspr r10, SPRN_IMMR /* Get current IMMR */
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mfspr r10, SPRN_IMMR /* Get current IMMR */
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rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
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rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT | _PAGE_NO_CACHE
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_PAGE_PRESENT | _PAGE_NO_CACHE
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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@ -696,7 +696,7 @@ DTLBMissLinear:
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li r11, MD_PS8MEG | MD_SVALID
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li r11, MD_PS8MEG | MD_SVALID
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mtspr SPRN_MD_TWC, r11
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mtspr SPRN_MD_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT
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_PAGE_PRESENT
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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@ -715,7 +715,7 @@ ITLBMissLinear:
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li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
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li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
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mtspr SPRN_MI_TWC, r11
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mtspr SPRN_MI_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT
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_PAGE_PRESENT
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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@ -67,7 +67,7 @@ void __init MMU_init_hw(void)
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/* PIN up to the 3 first 8Mb after IMMR in DTLB table */
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/* PIN up to the 3 first 8Mb after IMMR in DTLB table */
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#ifdef CONFIG_PIN_TLB_DATA
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#ifdef CONFIG_PIN_TLB_DATA
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unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
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unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
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unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY;
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unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY;
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#ifdef CONFIG_PIN_TLB_IMMR
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#ifdef CONFIG_PIN_TLB_IMMR
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int i = 29;
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int i = 29;
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#else
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#else
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@ -112,13 +112,8 @@ struct flag_info {
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static const struct flag_info flag_array[] = {
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static const struct flag_info flag_array[] = {
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{
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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.mask = _PAGE_USER | _PAGE_PRIVILEGED,
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.mask = _PAGE_PRIVILEGED,
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.val = 0,
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#else
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.mask = _PAGE_USER,
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.val = _PAGE_USER,
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.val = _PAGE_USER,
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#endif
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.set = "user",
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.set = "user",
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.clear = " ",
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.clear = " ",
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}, {
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}, {
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@ -229,10 +224,6 @@ static const struct flag_info flag_array[] = {
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.mask = _PAGE_SPECIAL,
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.mask = _PAGE_SPECIAL,
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.val = _PAGE_SPECIAL,
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.val = _PAGE_SPECIAL,
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.set = "special",
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.set = "special",
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}, {
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.mask = _PAGE_SHARED,
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.val = _PAGE_SHARED,
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.set = "shared",
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}
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}
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};
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};
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return 0;
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return 0;
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#else
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#else
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return (pte_val(pte) &
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) ==
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(_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER |
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_PAGE_PRIVILEGED)) ==
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(_PAGE_PRESENT | _PAGE_USER);
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(_PAGE_PRESENT | _PAGE_USER);
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#endif
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#endif
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}
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}
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/* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */
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/* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */
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flags &= ~(_PAGE_USER | _PAGE_EXEC);
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flags &= ~(_PAGE_USER | _PAGE_EXEC);
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flags |= _PAGE_PRIVILEGED;
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#ifdef _PAGE_BAP_SR
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/* _PAGE_USER contains _PAGE_BAP_SR on BookE using the new PTE format
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* which means that we just cleared supervisor access... oops ;-) This
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* restores it
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*/
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flags |= _PAGE_BAP_SR;
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#endif
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return __ioremap_caller(addr, size, flags, __builtin_return_address(0));
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return __ioremap_caller(addr, size, flags, __builtin_return_address(0));
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}
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}
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/*
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/*
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* Force kernel mapping.
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* Force kernel mapping.
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*/
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*/
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#if defined(CONFIG_PPC_BOOK3S_64)
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flags |= _PAGE_PRIVILEGED;
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#else
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flags &= ~_PAGE_USER;
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flags &= ~_PAGE_USER;
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#endif
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flags |= _PAGE_PRIVILEGED;
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#ifdef _PAGE_BAP_SR
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/* _PAGE_USER contains _PAGE_BAP_SR on BookE using the new PTE format
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* which means that we just cleared supervisor access... oops ;-) This
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* restores it
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*/
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flags |= _PAGE_BAP_SR;
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#endif
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if (ppc_md.ioremap)
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if (ppc_md.ioremap)
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return ppc_md.ioremap(addr, size, flags, caller);
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return ppc_md.ioremap(addr, size, flags, caller);
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