ARM: 6771/1: vexpress: add support for multiple core tiles
The current Versatile Express BSP defines the MACHINE_START macro in the core tile code. This patch moves this into the generic board code and introduces a method for determining the current tile at runtime, allowing the Kernel to have support for multiple tiles compiled in. Tile-specific functions are executed via a descriptor struct containing the correct implementations for the current tile. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Will Deacon
Russell King
parent
196f020fbb
commit
80b5efbd43
6 changed files with 112 additions and 63 deletions
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@ -17,9 +17,3 @@ struct amba_device name##_device = { \
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.irq = IRQ_##base, \
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/* .dma = DMA_##base,*/ \
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}
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struct map_desc;
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void v2m_map_io(struct map_desc *tile, size_t num);
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void v2m_init_early(void);
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extern struct sys_timer v2m_timer;
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@ -10,19 +10,17 @@
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#include <linux/amba/clcd.h>
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#include <linux/clkdev.h>
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#include <asm/pgtable.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/pmu.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <mach/ct-ca9x4.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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@ -58,7 +56,7 @@ static void __init ct_ca9x4_map_io(void)
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = MMIO_P2V(A9_MPCORE_TWD);
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#endif
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v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
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iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
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}
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static void __init ct_ca9x4_init_irq(void)
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@ -183,8 +181,6 @@ static struct platform_device pmu_device = {
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static void __init ct_ca9x4_init_early(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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v2m_init_early();
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}
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static void __init ct_ca9x4_init(void)
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@ -207,15 +203,34 @@ static void __init ct_ca9x4_init(void)
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platform_device_register(&pmu_device);
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}
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MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
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.boot_params = PLAT_PHYS_OFFSET + 0x00000100,
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.map_io = ct_ca9x4_map_io,
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.init_irq = ct_ca9x4_init_irq,
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.init_early = ct_ca9x4_init_early,
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#if 0
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.timer = &ct_ca9x4_timer,
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#else
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.timer = &v2m_timer,
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#ifdef CONFIG_SMP
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static void ct_ca9x4_init_cpu_map(void)
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{
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int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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}
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static void ct_ca9x4_smp_enable(unsigned int max_cpus)
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{
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int i;
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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scu_enable(MMIO_P2V(A9_MPCORE_SCU));
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}
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#endif
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.init_machine = ct_ca9x4_init,
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MACHINE_END
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struct ct_desc ct_ca9x4_desc __initdata = {
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.id = V2M_CT_ID_CA9,
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.name = "CA9x4",
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.map_io = ct_ca9x4_map_io,
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.init_early = ct_ca9x4_init_early,
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.init_irq = ct_ca9x4_init_irq,
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.init_tile = ct_ca9x4_init,
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#ifdef CONFIG_SMP
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.init_cpu_map = ct_ca9x4_init_cpu_map,
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.smp_enable = ct_ca9x4_smp_enable,
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#endif
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};
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@ -45,4 +45,6 @@
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#define IRQ_CT_CA9X4_PMU_CPU2 94
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#define IRQ_CT_CA9X4_PMU_CPU3 95
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extern struct ct_desc ct_ca9x4_desc;
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#endif
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@ -118,4 +118,26 @@
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int v2m_cfg_write(u32 devfn, u32 data);
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int v2m_cfg_read(u32 devfn, u32 *data);
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/*
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* Core tile IDs
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*/
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#define V2M_CT_ID_CA9 0x0c000191
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#define V2M_CT_ID_UNSUPPORTED 0xff000191
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#define V2M_CT_ID_MASK 0xff000fff
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struct ct_desc {
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u32 id;
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const char *name;
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void (*map_io)(void);
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void (*init_early)(void);
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void (*init_irq)(void);
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void (*init_tile)(void);
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#ifdef CONFIG_SMP
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void (*init_cpu_map)(void);
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void (*smp_enable)(unsigned int);
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#endif
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};
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extern struct ct_desc *ct_desc;
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#endif
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@ -13,10 +13,8 @@
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <mach/ct-ca9x4.h>
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#include <mach/motherboard.h>
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#define V2M_PA_CS7 0x10000000
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@ -24,47 +22,22 @@
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extern void versatile_secondary_startup(void);
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static void __iomem *scu_base_addr(void)
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{
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return MMIO_P2V(A9_MPCORE_SCU);
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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/* sanity check */
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"vexpress: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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ct_desc->init_cpu_map();
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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scu_enable(scu_base_addr());
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ct_desc->smp_enable(max_cpus);
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/*
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* Write the address of secondary startup into the
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@ -14,7 +14,9 @@
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#include <linux/usb/isp1760.h>
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#include <linux/clkdev.h>
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#include <asm/mach-types.h>
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#include <asm/sizes.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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@ -22,6 +24,7 @@
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/sp810.h>
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#include <mach/ct-ca9x4.h>
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#include <mach/motherboard.h>
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#include <plat/sched_clock.h>
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@ -43,14 +46,9 @@ static struct map_desc v2m_io_desc[] __initdata = {
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},
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};
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void __init v2m_map_io(struct map_desc *tile, size_t num)
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{
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iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
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iotable_init(tile, num);
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}
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void __init v2m_init_early(void)
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static void __init v2m_init_early(void)
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{
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ct_desc->init_early();
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versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
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}
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@ -71,7 +69,7 @@ static void __init v2m_timer_init(void)
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sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0);
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}
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struct sys_timer v2m_timer = {
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static struct sys_timer v2m_timer = {
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.init = v2m_timer_init,
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};
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@ -380,7 +378,44 @@ static void v2m_restart(char str, const char *cmd)
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printk(KERN_EMERG "Unable to reboot\n");
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}
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static int __init v2m_init(void)
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struct ct_desc *ct_desc;
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static struct ct_desc *ct_descs[] __initdata = {
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#ifdef CONFIG_ARCH_VEXPRESS_CA9X4
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&ct_ca9x4_desc,
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#endif
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};
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static void __init v2m_populate_ct_desc(void)
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{
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int i;
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u32 current_tile_id;
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ct_desc = NULL;
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current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
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for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
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if (ct_descs[i]->id == current_tile_id)
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ct_desc = ct_descs[i];
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if (!ct_desc)
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panic("vexpress: failed to populate core tile description "
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"for tile ID 0x%8x\n", current_tile_id);
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}
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static void __init v2m_map_io(void)
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{
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iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
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v2m_populate_ct_desc();
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ct_desc->map_io();
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}
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static void __init v2m_init_irq(void)
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{
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ct_desc->init_irq();
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}
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static void __init v2m_init(void)
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{
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int i;
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@ -399,6 +434,14 @@ static int __init v2m_init(void)
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pm_power_off = v2m_power_off;
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arm_pm_restart = v2m_restart;
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return 0;
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ct_desc->init_tile();
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}
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arch_initcall(v2m_init);
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MACHINE_START(VEXPRESS, "ARM-Versatile Express")
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.boot_params = PLAT_PHYS_OFFSET + 0x00000100,
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.map_io = v2m_map_io,
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.init_early = v2m_init_early,
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.init_irq = v2m_init_irq,
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.timer = &v2m_timer,
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.init_machine = v2m_init,
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MACHINE_END
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