Staging: comedi: Add spaces after commas where suggested by checkpatch.pl
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bill Pemberton
Greg Kroah-Hartman
parent
e473e9120b
commit
8086fff871
5 changed files with 71 additions and 71 deletions
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@ -37,16 +37,16 @@
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#include <linux/ioctl32.h> /* for (un)register_ioctl32_conversion */
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#endif
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#define COMEDI32_CHANINFO _IOR(CIO,3,comedi32_chaninfo)
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#define COMEDI32_RANGEINFO _IOR(CIO,8,comedi32_rangeinfo)
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#define COMEDI32_CHANINFO _IOR(CIO, 3, comedi32_chaninfo)
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#define COMEDI32_RANGEINFO _IOR(CIO, 8, comedi32_rangeinfo)
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/* N.B. COMEDI32_CMD and COMEDI_CMD ought to use _IOWR, not _IOR.
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* It's too late to change it now, but it only affects the command number. */
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#define COMEDI32_CMD _IOR(CIO,9,comedi32_cmd)
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#define COMEDI32_CMD _IOR(CIO, 9, comedi32_cmd)
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/* N.B. COMEDI32_CMDTEST and COMEDI_CMDTEST ought to use _IOWR, not _IOR.
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* It's too late to change it now, but it only affects the command number. */
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#define COMEDI32_CMDTEST _IOR(CIO,10,comedi32_cmd)
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#define COMEDI32_INSNLIST _IOR(CIO,11,comedi32_insnlist)
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#define COMEDI32_INSN _IOR(CIO,12,comedi32_insn)
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#define COMEDI32_CMDTEST _IOR(CIO, 10, comedi32_cmd)
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#define COMEDI32_INSNLIST _IOR(CIO, 11, comedi32_insnlist)
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#define COMEDI32_INSN _IOR(CIO, 12, comedi32_insn)
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typedef struct comedi32_chaninfo_struct {
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unsigned int subdev;
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@ -33,9 +33,9 @@
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#define PCIMIO_COMPAT
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#ifdef DEBUG_MITE
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#define MDPRINTK(format,args...) printk(format , ## args )
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#define MDPRINTK(format, args...) printk(format , ## args )
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#else
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#define MDPRINTK(format,args...)
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#define MDPRINTK(format, args...)
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#endif
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#define MAX_MITE_DMA_CHANNELS 8
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@ -366,11 +366,11 @@ typedef struct {
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#define DMA1_ACTIVE 0x04 /* DMA1 is active */
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/* Macros for accessing channel list bit array */
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#define CHAN_ARRAY_TEST(array,index) \
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#define CHAN_ARRAY_TEST(array, index) \
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(((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
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#define CHAN_ARRAY_SET(array,index) \
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#define CHAN_ARRAY_SET(array, index) \
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(((array)[(index)/8] |= 1 << ((index) & 0x7)))
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#define CHAN_ARRAY_CLEAR(array,index) \
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#define CHAN_ARRAY_CLEAR(array, index) \
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(((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
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/*
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@ -394,15 +394,15 @@ typedef struct {
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writel (0, devpriv->las0+LAS0_CGT_CLEAR)
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/* Reset channel gain table read and write pointers */
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#define RtdEnableCGT(dev,v) \
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#define RtdEnableCGT(dev, v) \
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writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
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/* Write channel gain table entry */
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#define RtdWriteCGTable(dev,v) \
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#define RtdWriteCGTable(dev, v) \
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writel (v, devpriv->las0+LAS0_CGT_WRITE)
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/* Write Channel Gain Latch */
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#define RtdWriteCGLatch(dev,v) \
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#define RtdWriteCGLatch(dev, v) \
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writel (v, devpriv->las0+LAS0_CGL_WRITE)
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/* Reset ADC FIFO */
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@ -410,39 +410,39 @@ typedef struct {
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writel (0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
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/* Set ADC start conversion source select (write only) */
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#define RtdAdcConversionSource(dev,v) \
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#define RtdAdcConversionSource(dev, v) \
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writel (v, devpriv->las0+LAS0_ADC_CONVERSION)
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/* Set burst start source select (write only) */
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#define RtdBurstStartSource(dev,v) \
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#define RtdBurstStartSource(dev, v) \
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writel (v, devpriv->las0+LAS0_BURST_START)
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/* Set Pacer start source select (write only) */
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#define RtdPacerStartSource(dev,v) \
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#define RtdPacerStartSource(dev, v) \
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writel (v, devpriv->las0+LAS0_PACER_START)
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/* Set Pacer stop source select (write only) */
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#define RtdPacerStopSource(dev,v) \
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#define RtdPacerStopSource(dev, v) \
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writel (v, devpriv->las0+LAS0_PACER_STOP)
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/* Set Pacer clock source select (write only) 0=external 1=internal */
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#define RtdPacerClockSource(dev,v) \
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#define RtdPacerClockSource(dev, v) \
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writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
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/* Set sample counter source select (write only) */
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#define RtdAdcSampleCounterSource(dev,v) \
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#define RtdAdcSampleCounterSource(dev, v) \
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writel (v, devpriv->las0+LAS0_ADC_SCNT_SRC)
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/* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
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#define RtdPacerTriggerMode(dev,v) \
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#define RtdPacerTriggerMode(dev, v) \
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writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
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/* Set About counter stop enable (write only) */
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#define RtdAboutStopEnable(dev,v) \
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#define RtdAboutStopEnable(dev, v) \
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writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
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/* Set external trigger polarity (write only) 0=positive edge, 1=negative */
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#define RtdTriggerPolarity(dev,v) \
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#define RtdTriggerPolarity(dev, v) \
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writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
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/* Start single ADC conversion */
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@ -473,15 +473,15 @@ typedef struct {
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readw (devpriv->las0+LAS0_IT)
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/* Interrupt mask */
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#define RtdInterruptMask(dev,v) \
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writew ((devpriv->intMask = (v)),devpriv->las0+LAS0_IT)
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#define RtdInterruptMask(dev, v) \
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writew ((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
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/* Interrupt status clear (only bits set in mask) */
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#define RtdInterruptClear(dev) \
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readw (devpriv->las0+LAS0_CLEAR)
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/* Interrupt clear mask */
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#define RtdInterruptClearMask(dev,v) \
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#define RtdInterruptClearMask(dev, v) \
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writew ((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
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/* Interrupt overrun status */
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@ -495,92 +495,92 @@ typedef struct {
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/* Pacer counter, 24bit */
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#define RtdPacerCount(dev) \
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readl (devpriv->las0+LAS0_PCLK)
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#define RtdPacerCounter(dev,v) \
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writel ((v) & 0xffffff,devpriv->las0+LAS0_PCLK)
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#define RtdPacerCounter(dev, v) \
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writel ((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
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/* Burst counter, 10bit */
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#define RtdBurstCount(dev) \
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readl (devpriv->las0+LAS0_BCLK)
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#define RtdBurstCounter(dev,v) \
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writel ((v) & 0x3ff,devpriv->las0+LAS0_BCLK)
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#define RtdBurstCounter(dev, v) \
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writel ((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
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/* Delay counter, 16bit */
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#define RtdDelayCount(dev) \
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readl (devpriv->las0+LAS0_DCLK)
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#define RtdDelayCounter(dev,v) \
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#define RtdDelayCounter(dev, v) \
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writel ((v) & 0xffff, devpriv->las0+LAS0_DCLK)
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/* About counter, 16bit */
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#define RtdAboutCount(dev) \
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readl (devpriv->las0+LAS0_ACNT)
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#define RtdAboutCounter(dev,v) \
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#define RtdAboutCounter(dev, v) \
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writel ((v) & 0xffff, devpriv->las0+LAS0_ACNT)
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/* ADC sample counter, 10bit */
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#define RtdAdcSampleCount(dev) \
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readl (devpriv->las0+LAS0_ADC_SCNT)
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#define RtdAdcSampleCounter(dev,v) \
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#define RtdAdcSampleCounter(dev, v) \
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writel ((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
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/* User Timer/Counter (8254) */
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#define RtdUtcCounterGet(dev,n) \
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#define RtdUtcCounterGet(dev, n) \
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readb (devpriv->las0 \
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+ ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
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#define RtdUtcCounterPut(dev,n,v) \
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#define RtdUtcCounterPut(dev, n, v) \
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writeb ((v) & 0xff, devpriv->las0 \
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+ ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
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/* Set UTC (8254) control byte */
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#define RtdUtcCtrlPut(dev,n,v) \
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#define RtdUtcCtrlPut(dev, n, v) \
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writeb (devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
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devpriv->las0 + LAS0_UTC_CTRL)
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/* Set UTCn clock source (write only) */
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#define RtdUtcClockSource(dev,n,v) \
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#define RtdUtcClockSource(dev, n, v) \
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writew (v, devpriv->las0 \
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+ ((n <= 0) ? LAS0_UTC0_CLOCK : \
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((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
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/* Set UTCn gate source (write only) */
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#define RtdUtcGateSource(dev,n,v) \
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#define RtdUtcGateSource(dev, n, v) \
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writew (v, devpriv->las0 \
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+ ((n <= 0) ? LAS0_UTC0_GATE : \
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((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
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/* User output N source select (write only) */
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#define RtdUsrOutSource(dev,n,v) \
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writel (v,devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : LAS0_UOUT1_SELECT))
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#define RtdUsrOutSource(dev, n, v) \
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writel (v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : LAS0_UOUT1_SELECT))
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/* Digital IO */
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#define RtdDio0Read(dev) \
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(readw (devpriv->las0+LAS0_DIO0) & 0xff)
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#define RtdDio0Write(dev,v) \
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#define RtdDio0Write(dev, v) \
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writew ((v) & 0xff, devpriv->las0+LAS0_DIO0)
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#define RtdDio1Read(dev) \
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(readw (devpriv->las0+LAS0_DIO1) & 0xff)
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#define RtdDio1Write(dev,v) \
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#define RtdDio1Write(dev, v) \
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writew ((v) & 0xff, devpriv->las0+LAS0_DIO1)
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#define RtdDioStatusRead(dev) \
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(readw (devpriv->las0+LAS0_DIO_STATUS) & 0xff)
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#define RtdDioStatusWrite(dev,v) \
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#define RtdDioStatusWrite(dev, v) \
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writew ((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
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#define RtdDio0CtrlRead(dev) \
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(readw (devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
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#define RtdDio0CtrlWrite(dev,v) \
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#define RtdDio0CtrlWrite(dev, v) \
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writew ((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
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/* Digital to Analog converter */
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/* Write one data value (sign + 12bit + marker bits) */
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/* Note: matches what DMA would put. Actual value << 3 */
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#define RtdDacFifoPut(dev,n,v) \
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#define RtdDacFifoPut(dev, n, v) \
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writew ((v), devpriv->las1 +(((n) == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO))
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/* Start single DAC conversion */
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#define RtdDacUpdate(dev,n) \
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#define RtdDacUpdate(dev, n) \
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writew (0, devpriv->las0 +(((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
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/* Start single DAC conversion on both DACs */
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@ -588,20 +588,20 @@ typedef struct {
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writew (0, devpriv->las0+LAS0_DAC)
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/* Set DAC output type and range */
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#define RtdDacRange(dev,n,v) \
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#define RtdDacRange(dev, n, v) \
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writew ((v) & 7, devpriv->las0 \
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+(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
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/* Reset DAC FIFO */
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#define RtdDacClearFifo(dev,n) \
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#define RtdDacClearFifo(dev, n) \
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writel (0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : LAS0_DAC2_RESET))
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/* Set source for DMA 0 (write only, shadow?) */
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#define RtdDma0Source(dev,n) \
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#define RtdDma0Source(dev, n) \
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writel ((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
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/* Set source for DMA 1 (write only, shadow?) */
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#define RtdDma1Source(dev,n) \
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#define RtdDma1Source(dev, n) \
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writel ((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
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/* Reset board state for DMA 0 */
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@ -615,51 +615,51 @@ typedef struct {
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/* PLX9080 interrupt mask and status */
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#define RtdPlxInterruptRead(dev) \
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readl (devpriv->lcfg+LCFG_ITCSR)
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#define RtdPlxInterruptWrite(dev,v) \
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#define RtdPlxInterruptWrite(dev, v) \
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writel (v, devpriv->lcfg+LCFG_ITCSR)
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/* Set mode for DMA 0 */
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#define RtdDma0Mode(dev,m) \
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#define RtdDma0Mode(dev, m) \
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writel ((m), devpriv->lcfg+LCFG_DMAMODE0)
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/* Set PCI address for DMA 0 */
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#define RtdDma0PciAddr(dev,a) \
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#define RtdDma0PciAddr(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMAPADR0)
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/* Set local address for DMA 0 */
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#define RtdDma0LocalAddr(dev,a) \
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#define RtdDma0LocalAddr(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMALADR0)
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/* Set byte count for DMA 0 */
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#define RtdDma0Count(dev,c) \
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#define RtdDma0Count(dev, c) \
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writel ((c), devpriv->lcfg+LCFG_DMASIZ0)
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/* Set next descriptor for DMA 0 */
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#define RtdDma0Next(dev,a) \
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#define RtdDma0Next(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMADPR0)
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/* Set mode for DMA 1 */
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#define RtdDma1Mode(dev,m) \
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#define RtdDma1Mode(dev, m) \
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writel ((m), devpriv->lcfg+LCFG_DMAMODE1)
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/* Set PCI address for DMA 1 */
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#define RtdDma1PciAddr(dev,a) \
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#define RtdDma1PciAddr(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMAADR1)
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/* Set local address for DMA 1 */
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#define RtdDma1LocalAddr(dev,a) \
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#define RtdDma1LocalAddr(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMALADR1)
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/* Set byte count for DMA 1 */
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#define RtdDma1Count(dev,c) \
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#define RtdDma1Count(dev, c) \
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writel ((c), devpriv->lcfg+LCFG_DMASIZ1)
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/* Set next descriptor for DMA 1 */
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#define RtdDma1Next(dev,a) \
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#define RtdDma1Next(dev, a) \
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writel ((a), devpriv->lcfg+LCFG_DMADPR1)
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/* Set control for DMA 0 (write only, shadow?) */
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#define RtdDma0Control(dev,n) \
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#define RtdDma0Control(dev, n) \
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writeb (devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
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/* Get status for DMA 0 */
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@ -667,7 +667,7 @@ typedef struct {
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readb (devpriv->lcfg+LCFG_DMACSR0)
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/* Set control for DMA 1 (write only, shadow?) */
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#define RtdDma1Control(dev,n) \
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#define RtdDma1Control(dev, n) \
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writeb (devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
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/* Get status for DMA 1 */
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@ -454,7 +454,7 @@ static enc_private enc_private_data[] = {
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/* enab/disable a function or test status bit(s) that are accessed */
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/* through Main Control Registers 1 or 2. */
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#define MC_ENABLE( REGADRS, CTRLWORD ) writel( ( (uint32_t)( CTRLWORD ) << 16 ) | (uint32_t)( CTRLWORD ),devpriv->base_addr+( REGADRS ) )
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#define MC_ENABLE( REGADRS, CTRLWORD ) writel( ( (uint32_t)( CTRLWORD ) << 16 ) | (uint32_t)( CTRLWORD ), devpriv->base_addr+( REGADRS ) )
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#define MC_DISABLE( REGADRS, CTRLWORD ) writel( (uint32_t)( CTRLWORD ) << 16 , devpriv->base_addr+( REGADRS ) )
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@ -462,7 +462,7 @@ static enc_private enc_private_data[] = {
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/* #define WR7146(REGARDS,CTRLWORD)
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writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
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#define WR7146(REGARDS,CTRLWORD) writel(CTRLWORD,devpriv->base_addr+(REGARDS))
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#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
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/* #define RR7146(REGARDS)
|
||||
readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
|
||||
|
|
@ -475,9 +475,9 @@ static enc_private enc_private_data[] = {
|
|||
#define SETVECT( VECTNUM, VECTVAL ) WR7146(VECTPORT( VECTNUM ), (VECTVAL))
|
||||
|
||||
/* Code macros used for constructing I2C command bytes. */
|
||||
#define I2C_B2(ATTR,VAL) ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
|
||||
#define I2C_B1(ATTR,VAL) ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
|
||||
#define I2C_B0(ATTR,VAL) ( ( (ATTR) << 2 ) | ( (VAL) << 8 ) )
|
||||
#define I2C_B2(ATTR, VAL) ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
|
||||
#define I2C_B1(ATTR, VAL) ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
|
||||
#define I2C_B0(ATTR, VAL) ( ( (ATTR) << 2 ) | ( (VAL) << 8 ) )
|
||||
|
||||
static const comedi_lrange s626_range_table = { 2, {
|
||||
RANGE(-5, 5),
|
||||
|
|
|
|||
|
|
@ -470,9 +470,9 @@
|
|||
#define I2CW ( devpriv->I2CAdrs )
|
||||
|
||||
/* Code macros used for constructing I2C command bytes. */
|
||||
#define I2C_B2(ATTR,VAL) ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
|
||||
#define I2C_B1(ATTR,VAL) ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
|
||||
#define I2C_B0(ATTR,VAL) ( ( (ATTR) << 2 ) | ( (VAL) << 8 ) )
|
||||
#define I2C_B2(ATTR, VAL) ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
|
||||
#define I2C_B1(ATTR, VAL) ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
|
||||
#define I2C_B0(ATTR, VAL) ( ( (ATTR) << 2 ) | ( (VAL) << 8 ) )
|
||||
|
||||
/* oldest */
|
||||
#define P_DEBICFGq 0x007C /* DEBI configuration. */
|
||||
|
|
|
|||
Loading…
Reference in a new issue