viafb: accel.c, accel.h
2D and HW cursor stuff of viafb driver. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Joseph Chan <josephchan@via.com.tw> Cc: Krzysztof Helt <krzysztof.h1@poczta.fm> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Joseph Chan
Linus Torvalds
parent
6bde3ed98d
commit
801b8a8c91
2 changed files with 448 additions and 0 deletions
279
drivers/video/via/accel.c
Normal file
279
drivers/video/via/accel.c
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "global.h"
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void viafb_init_accel(void)
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{
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viaparinfo->fbmem_free -= CURSOR_SIZE;
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viaparinfo->cursor_start = viaparinfo->fbmem_free;
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viaparinfo->fbmem_used += CURSOR_SIZE;
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/* Reverse 8*1024 memory space for cursor image */
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viaparinfo->fbmem_free -= (CURSOR_SIZE + VQ_SIZE);
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viaparinfo->VQ_start = viaparinfo->fbmem_free;
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viaparinfo->VQ_end = viaparinfo->VQ_start + VQ_SIZE - 1;
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viaparinfo->fbmem_used += (CURSOR_SIZE + VQ_SIZE); }
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void viafb_init_2d_engine(void)
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{
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u32 dwVQStartAddr, dwVQEndAddr;
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u32 dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
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/* init 2D engine regs to reset 2D engine */
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writel(0x0, viaparinfo->io_virt + VIA_REG_GEMODE);
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writel(0x0, viaparinfo->io_virt + VIA_REG_SRCPOS);
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writel(0x0, viaparinfo->io_virt + VIA_REG_DSTPOS);
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writel(0x0, viaparinfo->io_virt + VIA_REG_DIMENSION);
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writel(0x0, viaparinfo->io_virt + VIA_REG_PATADDR);
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writel(0x0, viaparinfo->io_virt + VIA_REG_FGCOLOR);
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writel(0x0, viaparinfo->io_virt + VIA_REG_BGCOLOR);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPTL);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPBR);
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writel(0x0, viaparinfo->io_virt + VIA_REG_OFFSET);
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writel(0x0, viaparinfo->io_virt + VIA_REG_KEYCONTROL);
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writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
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writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
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writel(0x0, viaparinfo->io_virt + VIA_REG_PITCH);
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writel(0x0, viaparinfo->io_virt + VIA_REG_MONOPAT1);
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/* Init AGP and VQ regs */
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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writel(0x00100000, viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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writel(0x680A0000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(0x02000000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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break;
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default:
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writel(0x00100000, viaparinfo->io_virt + VIA_REG_TRANSET);
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writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x00333004, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x60000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x61000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x62000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x63000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x64000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x7D000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0xFE020000, viaparinfo->io_virt + VIA_REG_TRANSET);
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writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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break;
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}
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if (viaparinfo->VQ_start != 0) {
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/* Enable VQ */
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dwVQStartAddr = viaparinfo->VQ_start;
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dwVQEndAddr = viaparinfo->VQ_end;
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dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
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dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
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dwVQStartEndH = 0x52000000 |
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((dwVQStartAddr & 0xFF000000) >> 24) |
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((dwVQEndAddr & 0xFF000000) >> 16);
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dwVQLen = 0x53000000 | (VQ_SIZE >> 3);
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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dwVQStartL |= 0x20000000;
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dwVQEndL |= 0x20000000;
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dwVQStartEndH |= 0x20000000;
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dwVQLen |= 0x20000000;
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break;
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default:
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break;
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}
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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writel(0x00100000,
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viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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writel(dwVQStartEndH,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(dwVQStartL,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(dwVQEndL,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(dwVQLen,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(0x74301001,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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writel(0x00000000,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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break;
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default:
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writel(0x00FE0000,
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viaparinfo->io_virt + VIA_REG_TRANSET);
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writel(0x080003FE,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0A00027C,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0B000260,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0C000274,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0D000264,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0E000000,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x0F000020,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x1000027E,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x110002FE,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x200F0060,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x00000006,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x40008C0F,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x44000000,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x45080C04,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x46800408,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(dwVQStartEndH,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(dwVQStartL,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(dwVQEndL,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(dwVQLen,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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break;
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}
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} else {
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/* Disable VQ */
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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writel(0x00100000,
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viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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writel(0x74301000,
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viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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break;
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default:
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writel(0x00FE0000,
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viaparinfo->io_virt + VIA_REG_TRANSET);
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writel(0x00000004,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x40008C0F,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x44000000,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x45080C04,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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writel(0x46800408,
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viaparinfo->io_virt + VIA_REG_TRANSPACE);
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break;
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}
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}
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viafb_set_2d_color_depth(viaparinfo->bpp);
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writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
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writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
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writel(VIA_PITCH_ENABLE |
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(((viaparinfo->hres *
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viaparinfo->bpp >> 3) >> 3) | (((viaparinfo->hres *
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viaparinfo->
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bpp >> 3) >> 3) << 16)),
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viaparinfo->io_virt + VIA_REG_PITCH);
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}
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void viafb_set_2d_color_depth(int bpp)
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{
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u32 dwGEMode;
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dwGEMode = readl(viaparinfo->io_virt + 0x04) & 0xFFFFFCFF;
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switch (bpp) {
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case 16:
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dwGEMode |= VIA_GEM_16bpp;
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break;
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case 32:
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dwGEMode |= VIA_GEM_32bpp;
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break;
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default:
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dwGEMode |= VIA_GEM_8bpp;
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break;
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}
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/* Set BPP and Pitch */
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writel(dwGEMode, viaparinfo->io_virt + VIA_REG_GEMODE);
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}
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void viafb_hw_cursor_init(void)
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{
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/* Set Cursor Image Base Address */
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writel(viaparinfo->cursor_start,
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viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
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writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
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}
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void viafb_show_hw_cursor(struct fb_info *info, int Status)
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{
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u32 temp;
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u32 iga_path = ((struct viafb_par *)(info->par))->iga_path;
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temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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switch (Status) {
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case HW_Cursor_ON:
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temp |= 0x1;
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break;
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case HW_Cursor_OFF:
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temp &= 0xFFFFFFFE;
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break;
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}
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switch (iga_path) {
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case IGA2:
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temp |= 0x80000000;
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break;
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case IGA1:
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default:
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temp &= 0x7FFFFFFF;
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}
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writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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}
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int viafb_wait_engine_idle(void)
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{
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int loop = 0;
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while (!(readl(viaparinfo->io_virt + VIA_REG_STATUS) &
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VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
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cpu_relax();
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while ((readl(viaparinfo->io_virt + VIA_REG_STATUS) &
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(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
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(loop++ < MAXLOOP))
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cpu_relax();
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return loop >= MAXLOOP;
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}
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169
drivers/video/via/accel.h
Normal file
169
drivers/video/via/accel.h
Normal file
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public
|
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* License as published by the Free Software Foundation;
|
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* either version 2, or (at your option) any later version.
|
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|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
|
||||
* the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
* A PARTICULAR PURPOSE.See the GNU General Public License
|
||||
* for more details.
|
||||
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.,
|
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ACCEL_H__
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#define __ACCEL_H__
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#define FB_ACCEL_VIA_UNICHROME 50
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/* MMIO Base Address Definition */
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#define MMIO_VGABASE 0x8000
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#define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
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#define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
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#define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
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#define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
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/* HW Cursor Status Define */
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#define HW_Cursor_ON 0
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#define HW_Cursor_OFF 1
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#define CURSOR_SIZE (8 * 1024)
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#define VQ_SIZE (256 * 1024)
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#define VIA_MMIO_BLTBASE 0x200000
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#define VIA_MMIO_BLTSIZE 0x200000
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/* Defines for 2D registers */
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#define VIA_REG_GECMD 0x000
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#define VIA_REG_GEMODE 0x004
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#define VIA_REG_SRCPOS 0x008
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#define VIA_REG_DSTPOS 0x00C
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/* width and height */
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#define VIA_REG_DIMENSION 0x010
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#define VIA_REG_PATADDR 0x014
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#define VIA_REG_FGCOLOR 0x018
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#define VIA_REG_BGCOLOR 0x01C
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/* top and left of clipping */
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#define VIA_REG_CLIPTL 0x020
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/* bottom and right of clipping */
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#define VIA_REG_CLIPBR 0x024
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#define VIA_REG_OFFSET 0x028
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/* color key control */
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#define VIA_REG_KEYCONTROL 0x02C
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#define VIA_REG_SRCBASE 0x030
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#define VIA_REG_DSTBASE 0x034
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/* pitch of src and dst */
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#define VIA_REG_PITCH 0x038
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#define VIA_REG_MONOPAT0 0x03C
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#define VIA_REG_MONOPAT1 0x040
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/* from 0x100 to 0x1ff */
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#define VIA_REG_COLORPAT 0x100
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/* VIA_REG_PITCH(0x38): Pitch Setting */
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#define VIA_PITCH_ENABLE 0x80000000
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/* defines for VIA HW cursor registers */
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#define VIA_REG_CURSOR_MODE 0x2D0
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#define VIA_REG_CURSOR_POS 0x2D4
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#define VIA_REG_CURSOR_ORG 0x2D8
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#define VIA_REG_CURSOR_BG 0x2DC
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#define VIA_REG_CURSOR_FG 0x2E0
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/* VIA_REG_GEMODE(0x04): GE mode */
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#define VIA_GEM_8bpp 0x00000000
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#define VIA_GEM_16bpp 0x00000100
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#define VIA_GEM_32bpp 0x00000300
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/* VIA_REG_GECMD(0x00): 2D Engine Command */
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#define VIA_GEC_NOOP 0x00000000
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#define VIA_GEC_BLT 0x00000001
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#define VIA_GEC_LINE 0x00000005
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/* Rotate Command */
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#define VIA_GEC_ROT 0x00000008
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#define VIA_GEC_SRC_XY 0x00000000
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#define VIA_GEC_SRC_LINEAR 0x00000010
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#define VIA_GEC_DST_XY 0x00000000
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#define VIA_GEC_DST_LINRAT 0x00000020
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#define VIA_GEC_SRC_FB 0x00000000
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#define VIA_GEC_SRC_SYS 0x00000040
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#define VIA_GEC_DST_FB 0x00000000
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#define VIA_GEC_DST_SYS 0x00000080
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/* source is mono */
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#define VIA_GEC_SRC_MONO 0x00000100
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/* pattern is mono */
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#define VIA_GEC_PAT_MONO 0x00000200
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||||
/* mono src is opaque */
|
||||
#define VIA_GEC_MSRC_OPAQUE 0x00000000
|
||||
/* mono src is transparent */
|
||||
#define VIA_GEC_MSRC_TRANS 0x00000400
|
||||
/* pattern is in frame buffer */
|
||||
#define VIA_GEC_PAT_FB 0x00000000
|
||||
/* pattern is from reg setting */
|
||||
#define VIA_GEC_PAT_REG 0x00000800
|
||||
|
||||
#define VIA_GEC_CLIP_DISABLE 0x00000000
|
||||
#define VIA_GEC_CLIP_ENABLE 0x00001000
|
||||
|
||||
#define VIA_GEC_FIXCOLOR_PAT 0x00002000
|
||||
|
||||
#define VIA_GEC_INCX 0x00000000
|
||||
#define VIA_GEC_DECY 0x00004000
|
||||
#define VIA_GEC_INCY 0x00000000
|
||||
#define VIA_GEC_DECX 0x00008000
|
||||
/* mono pattern is opaque */
|
||||
#define VIA_GEC_MPAT_OPAQUE 0x00000000
|
||||
/* mono pattern is transparent */
|
||||
#define VIA_GEC_MPAT_TRANS 0x00010000
|
||||
|
||||
#define VIA_GEC_MONO_UNPACK 0x00000000
|
||||
#define VIA_GEC_MONO_PACK 0x00020000
|
||||
#define VIA_GEC_MONO_DWORD 0x00000000
|
||||
#define VIA_GEC_MONO_WORD 0x00040000
|
||||
#define VIA_GEC_MONO_BYTE 0x00080000
|
||||
|
||||
#define VIA_GEC_LASTPIXEL_ON 0x00000000
|
||||
#define VIA_GEC_LASTPIXEL_OFF 0x00100000
|
||||
#define VIA_GEC_X_MAJOR 0x00000000
|
||||
#define VIA_GEC_Y_MAJOR 0x00200000
|
||||
#define VIA_GEC_QUICK_START 0x00800000
|
||||
|
||||
/* defines for VIA 3D registers */
|
||||
#define VIA_REG_STATUS 0x400
|
||||
#define VIA_REG_CR_TRANSET 0x41C
|
||||
#define VIA_REG_CR_TRANSPACE 0x420
|
||||
#define VIA_REG_TRANSET 0x43C
|
||||
#define VIA_REG_TRANSPACE 0x440
|
||||
|
||||
/* VIA_REG_STATUS(0x400): Engine Status */
|
||||
|
||||
/* Command Regulator is busy */
|
||||
#define VIA_CMD_RGTR_BUSY 0x00000080
|
||||
/* 2D Engine is busy */
|
||||
#define VIA_2D_ENG_BUSY 0x00000002
|
||||
/* 3D Engine is busy */
|
||||
#define VIA_3D_ENG_BUSY 0x00000001
|
||||
/* Virtual Queue is busy */
|
||||
#define VIA_VR_QUEUE_BUSY 0x00020000
|
||||
|
||||
#define MAXLOOP 0xFFFFFF
|
||||
|
||||
void viafb_init_accel(void);
|
||||
void viafb_init_2d_engine(void);
|
||||
void set_2d_color_depth(int);
|
||||
void viafb_hw_cursor_init(void);
|
||||
void viafb_show_hw_cursor(struct fb_info *info, int Status); int
|
||||
viafb_wait_engine_idle(void); void viafb_set_2d_color_depth(int bpp);
|
||||
|
||||
#endif /* __ACCEL_H__ */
|
||||
Loading…
Reference in a new issue