[PATCH] ARM: 2829/1: S3C2410 - split s3c2440 irq specifics from core irq.c
Patch from Ben Dooks Remove the need for the #ifdefs and place the IRQ handling code for the s3c2440 into a new file, which is only compiled when the s3c2440 cpu support is enabled. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
5730b7d652
commit
7fcc113c30
4 changed files with 312 additions and 255 deletions
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@ -23,6 +23,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
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# S3C2440 support
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obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
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# machine specific support
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@ -45,6 +45,9 @@
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*
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* 28-Jun-2005 Ben Dooks
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* Mark IRQ_LCD valid
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*
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* 25-Jul-2005 Ben Dooks
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* Split the S3C2440 IRQ code to seperate file
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*/
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#include <linux/init.h>
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@ -65,11 +68,7 @@
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#include "cpu.h"
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#include "pm.h"
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#define irqdbf(x...)
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#define irqdbf2(x...)
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#define EXTINT_OFF (IRQ_EINT4 - 4)
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#include "irq.h"
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/* wakeup irq control */
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@ -181,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
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__raw_writel(mask, S3C2410_INTMSK);
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}
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static struct irqchip s3c_irq_level_chip = {
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struct irqchip s3c_irq_level_chip = {
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.ack = s3c_irq_maskack,
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.mask = s3c_irq_mask,
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.unmask = s3c_irq_unmask,
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@ -370,84 +369,6 @@ static struct irqchip s3c_irq_eint0t4 = {
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#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
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#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
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static inline void
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s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
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int subcheck)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
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/* check to see if we need to mask the parent IRQ */
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if ((submask & subcheck) == subcheck) {
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__raw_writel(mask | parentbit, S3C2410_INTMSK);
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}
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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}
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static inline void
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s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
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mask &= ~parentbit;
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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__raw_writel(mask, S3C2410_INTMSK);
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}
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static inline void
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s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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s3c_irqsub_mask(irqno, parentmask, group);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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static inline void
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s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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/* UART0 */
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@ -794,174 +715,3 @@ void __init s3c24xx_init_irq(void)
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irqdbf("s3c2410: registered interrupt handlers\n");
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}
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/* s3c2440 irq code
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*/
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#ifdef CONFIG_CPU_S3C2440
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/* WDT/AC97 */
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static void s3c_irq_demux_wdtac97(unsigned int irq,
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struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int subsrc, submsk;
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struct irqdesc *mydesc;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 13;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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mydesc = irq_desc + IRQ_S3C2440_WDT;
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mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
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}
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if (subsrc & 2) {
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mydesc = irq_desc + IRQ_S3C2440_AC97;
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mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
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}
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}
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}
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#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
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static void
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s3c_irq_wdtac97_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
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}
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static void
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s3c_irq_wdtac97_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_WDT);
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}
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static void
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s3c_irq_wdtac97_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
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}
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static struct irqchip s3c_irq_wdtac97 = {
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.mask = s3c_irq_wdtac97_mask,
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.unmask = s3c_irq_wdtac97_unmask,
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.ack = s3c_irq_wdtac97_ack,
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};
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/* camera irq */
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static void s3c_irq_demux_cam(unsigned int irq,
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struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int subsrc, submsk;
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struct irqdesc *mydesc;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 11;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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mydesc = irq_desc + IRQ_S3C2440_CAM_C;
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mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
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}
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if (subsrc & 2) {
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mydesc = irq_desc + IRQ_S3C2440_CAM_P;
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mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
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}
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}
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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static void
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s3c_irq_cam_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
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}
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static void
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s3c_irq_cam_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_CAM);
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}
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static void
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s3c_irq_cam_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
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}
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static struct irqchip s3c_irq_cam = {
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.mask = s3c_irq_cam_mask,
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.unmask = s3c_irq_cam_unmask,
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.ack = s3c_irq_cam_ack,
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};
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static int s3c2440_irq_add(struct sys_device *sysdev)
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{
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unsigned int irqno;
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printk("S3C2440: IRQ Support\n");
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set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
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set_irq_handler(IRQ_NFCON, do_level_IRQ);
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set_irq_flags(IRQ_NFCON, IRQF_VALID);
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/* add new chained handler for wdt, ac7 */
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set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
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set_irq_handler(IRQ_WDT, do_level_IRQ);
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set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
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for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
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set_irq_chip(irqno, &s3c_irq_wdtac97);
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set_irq_handler(irqno, do_level_IRQ);
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set_irq_flags(irqno, IRQF_VALID);
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}
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/* add chained handler for camera */
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set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
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set_irq_handler(IRQ_CAM, do_level_IRQ);
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set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
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for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
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set_irq_chip(irqno, &s3c_irq_cam);
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set_irq_handler(irqno, do_level_IRQ);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct sysdev_driver s3c2440_irq_driver = {
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.add = s3c2440_irq_add,
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};
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static int s3c24xx_irq_driver(void)
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{
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return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
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}
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arch_initcall(s3c24xx_irq_driver);
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#endif /* CONFIG_CPU_S3C2440 */
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99
arch/arm/mach-s3c2410/irq.h
Normal file
99
arch/arm/mach-s3c2410/irq.h
Normal file
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@ -0,0 +1,99 @@
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/* arch/arm/mach-s3c2410/irq.h
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Header file for S3C24XX CPU IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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*/
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#define irqdbf(x...)
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#define irqdbf2(x...)
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#define EXTINT_OFF (IRQ_EINT4 - 4)
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extern struct irqchip s3c_irq_level_chip;
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static inline void
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s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
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int subcheck)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
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/* check to see if we need to mask the parent IRQ */
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if ((submask & subcheck) == subcheck) {
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__raw_writel(mask | parentbit, S3C2410_INTMSK);
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}
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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}
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static inline void
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s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
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mask &= ~parentbit;
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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__raw_writel(mask, S3C2410_INTMSK);
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}
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static inline void
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s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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s3c_irqsub_mask(irqno, parentmask, group);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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static inline void
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s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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207
arch/arm/mach-s3c2410/s3c2440-irq.c
Normal file
207
arch/arm/mach-s3c2410/s3c2440-irq.c
Normal file
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@ -0,0 +1,207 @@
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/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
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*
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* Copyright (c) 2003,2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Changelog:
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* 25-Jul-2005 BJD Split from irq.c
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/ptrace.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/regs-irq.h>
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#include <asm/arch/regs-gpio.h>
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#include "cpu.h"
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#include "pm.h"
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#include "irq.h"
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/* WDT/AC97 */
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static void s3c_irq_demux_wdtac97(unsigned int irq,
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struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int subsrc, submsk;
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struct irqdesc *mydesc;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
|
||||
|
||||
subsrc &= ~submsk;
|
||||
subsrc >>= 13;
|
||||
subsrc &= 3;
|
||||
|
||||
if (subsrc != 0) {
|
||||
if (subsrc & 1) {
|
||||
mydesc = irq_desc + IRQ_S3C2440_WDT;
|
||||
mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
|
||||
}
|
||||
if (subsrc & 2) {
|
||||
mydesc = irq_desc + IRQ_S3C2440_AC97;
|
||||
mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
|
||||
|
||||
static void
|
||||
s3c_irq_wdtac97_mask(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
|
||||
}
|
||||
|
||||
static void
|
||||
s3c_irq_wdtac97_unmask(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_unmask(irqno, INTMSK_WDT);
|
||||
}
|
||||
|
||||
static void
|
||||
s3c_irq_wdtac97_ack(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
|
||||
}
|
||||
|
||||
static struct irqchip s3c_irq_wdtac97 = {
|
||||
.mask = s3c_irq_wdtac97_mask,
|
||||
.unmask = s3c_irq_wdtac97_unmask,
|
||||
.ack = s3c_irq_wdtac97_ack,
|
||||
};
|
||||
|
||||
/* camera irq */
|
||||
|
||||
static void s3c_irq_demux_cam(unsigned int irq,
|
||||
struct irqdesc *desc,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
unsigned int subsrc, submsk;
|
||||
struct irqdesc *mydesc;
|
||||
|
||||
/* read the current pending interrupts, and the mask
|
||||
* for what it is available */
|
||||
|
||||
subsrc = __raw_readl(S3C2410_SUBSRCPND);
|
||||
submsk = __raw_readl(S3C2410_INTSUBMSK);
|
||||
|
||||
subsrc &= ~submsk;
|
||||
subsrc >>= 11;
|
||||
subsrc &= 3;
|
||||
|
||||
if (subsrc != 0) {
|
||||
if (subsrc & 1) {
|
||||
mydesc = irq_desc + IRQ_S3C2440_CAM_C;
|
||||
mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
|
||||
}
|
||||
if (subsrc & 2) {
|
||||
mydesc = irq_desc + IRQ_S3C2440_CAM_P;
|
||||
mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
|
||||
|
||||
static void
|
||||
s3c_irq_cam_mask(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
|
||||
}
|
||||
|
||||
static void
|
||||
s3c_irq_cam_unmask(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_unmask(irqno, INTMSK_CAM);
|
||||
}
|
||||
|
||||
static void
|
||||
s3c_irq_cam_ack(unsigned int irqno)
|
||||
{
|
||||
s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
|
||||
}
|
||||
|
||||
static struct irqchip s3c_irq_cam = {
|
||||
.mask = s3c_irq_cam_mask,
|
||||
.unmask = s3c_irq_cam_unmask,
|
||||
.ack = s3c_irq_cam_ack,
|
||||
};
|
||||
|
||||
static int s3c2440_irq_add(struct sys_device *sysdev)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
printk("S3C2440: IRQ Support\n");
|
||||
|
||||
set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
|
||||
set_irq_handler(IRQ_NFCON, do_level_IRQ);
|
||||
set_irq_flags(IRQ_NFCON, IRQF_VALID);
|
||||
|
||||
/* add new chained handler for wdt, ac7 */
|
||||
|
||||
set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
|
||||
set_irq_handler(IRQ_WDT, do_level_IRQ);
|
||||
set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
|
||||
|
||||
for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
|
||||
set_irq_chip(irqno, &s3c_irq_wdtac97);
|
||||
set_irq_handler(irqno, do_level_IRQ);
|
||||
set_irq_flags(irqno, IRQF_VALID);
|
||||
}
|
||||
|
||||
/* add chained handler for camera */
|
||||
|
||||
set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
|
||||
set_irq_handler(IRQ_CAM, do_level_IRQ);
|
||||
set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
|
||||
|
||||
for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
|
||||
set_irq_chip(irqno, &s3c_irq_cam);
|
||||
set_irq_handler(irqno, do_level_IRQ);
|
||||
set_irq_flags(irqno, IRQF_VALID);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_driver s3c2440_irq_driver = {
|
||||
.add = s3c2440_irq_add,
|
||||
};
|
||||
|
||||
static int s3c24xx_irq_driver(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c24xx_irq_driver);
|
||||
|
||||
Loading…
Reference in a new issue