[SUNGEM]: Unbreak Sun GEM chips.
Revert: 40727198bf
These PHY changes hang the sungem driver on startup with Sun chips on
sparc64. Hopefully we can redo these changes in a way that doesn't
break non-Apple systems.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
3fa97c9db4
commit
7fb76aa07f
2 changed files with 28 additions and 35 deletions
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@ -910,18 +910,16 @@ core99_gmac_phy_reset(struct device_node *node, long param, long value)
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macio->type != macio_intrepid)
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return -ENODEV;
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printk(KERN_DEBUG "Hard reset of PHY chip ...\n");
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LOCK(flags);
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MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
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(void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
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UNLOCK(flags);
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msleep(10);
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mdelay(10);
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LOCK(flags);
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MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
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KEYLARGO_GPIO_OUTOUT_DATA);
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UNLOCK(flags);
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msleep(10);
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mdelay(10);
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return 0;
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}
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@ -1653,40 +1653,36 @@ static void gem_init_rings(struct gem *gp)
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/* Init PHY interface and start link poll state machine */
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static void gem_init_phy(struct gem *gp)
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{
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u32 mif_cfg;
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u32 mifcfg;
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/* Revert MIF CFG setting done on stop_phy */
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mif_cfg = readl(gp->regs + MIF_CFG);
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mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
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mif_cfg |= MIF_CFG_MDI0;
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writel(mif_cfg, gp->regs + MIF_CFG);
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writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
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writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
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mifcfg = readl(gp->regs + MIF_CFG);
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mifcfg &= ~MIF_CFG_BBMODE;
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writel(mifcfg, gp->regs + MIF_CFG);
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if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
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int i;
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u16 ctrl;
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#ifdef CONFIG_PPC_PMAC
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pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
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#endif
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/* Some PHYs used by apple have problem getting back
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* to us, we do an additional reset here
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/* Those delay sucks, the HW seem to love them though, I'll
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* serisouly consider breaking some locks here to be able
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* to schedule instead
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*/
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phy_write(gp, MII_BMCR, BMCR_RESET);
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for (i = 0; i < 50; i++) {
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if ((phy_read(gp, MII_BMCR) & BMCR_RESET) == 0)
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for (i = 0; i < 3; i++) {
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#ifdef CONFIG_PPC_PMAC
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pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
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msleep(20);
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#endif
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/* Some PHYs used by apple have problem getting back to us,
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* we do an additional reset here
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*/
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phy_write(gp, MII_BMCR, BMCR_RESET);
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msleep(20);
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if (phy_read(gp, MII_BMCR) != 0xffff)
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break;
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msleep(10);
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if (i == 2)
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printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
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gp->dev->name);
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}
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if (i == 50)
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printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
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gp->dev->name);
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/* Make sure isolate is off */
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ctrl = phy_read(gp, MII_BMCR);
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if (ctrl & BMCR_ISOLATE)
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phy_write(gp, MII_BMCR, ctrl & ~BMCR_ISOLATE);
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}
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if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
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@ -2123,7 +2119,7 @@ static void gem_reinit_chip(struct gem *gp)
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/* Must be invoked with no lock held. */
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static void gem_stop_phy(struct gem *gp, int wol)
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{
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u32 mif_cfg;
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u32 mifcfg;
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unsigned long flags;
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/* Let the chip settle down a bit, it seems that helps
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@ -2134,9 +2130,9 @@ static void gem_stop_phy(struct gem *gp, int wol)
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/* Make sure we aren't polling PHY status change. We
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* don't currently use that feature though
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*/
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mif_cfg = readl(gp->regs + MIF_CFG);
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mif_cfg &= ~MIF_CFG_POLL;
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writel(mif_cfg, gp->regs + MIF_CFG);
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mifcfg = readl(gp->regs + MIF_CFG);
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mifcfg &= ~MIF_CFG_POLL;
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writel(mifcfg, gp->regs + MIF_CFG);
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if (wol && gp->has_wol) {
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unsigned char *e = &gp->dev->dev_addr[0];
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@ -2186,8 +2182,7 @@ static void gem_stop_phy(struct gem *gp, int wol)
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/* According to Apple, we must set the MDIO pins to this begnign
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* state or we may 1) eat more current, 2) damage some PHYs
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*/
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mif_cfg = 0;
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writel(mif_cfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
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writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
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writel(0, gp->regs + MIF_BBCLK);
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writel(0, gp->regs + MIF_BBDATA);
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writel(0, gp->regs + MIF_BBOENAB);
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