dmaengine/ste_dma40: support pm in dma40
This patch adds power management support to the dma40 driver. The DMA registers are backed up and restored, during suspend/resume. Also flags to track the dma usage have been introduced to facilitate this. Patch also includes few other minor changes, related to formatting, comments. Signed-off-by: Narayanan G <narayanan.gopalakrishnan@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Narayanan G
Vinod Koul
parent
ca21a146a4
commit
7fb3e75e18
2 changed files with 259 additions and 19 deletions
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@ -14,6 +14,8 @@
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/err.h>
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#include <linux/amba/bus.h>
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@ -32,6 +34,9 @@
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/* Maximum iterations taken before giving up suspending a channel */
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#define D40_SUSPEND_MAX_IT 500
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/* Milliseconds */
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#define DMA40_AUTOSUSPEND_DELAY 100
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/* Hardware requirement on LCLA alignment */
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#define LCLA_ALIGNMENT 0x40000
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@ -62,6 +67,55 @@ enum d40_command {
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D40_DMA_SUSPENDED = 3
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};
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/*
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* These are the registers that has to be saved and later restored
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* when the DMA hw is powered off.
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* TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
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*/
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static u32 d40_backup_regs[] = {
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D40_DREG_LCPA,
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D40_DREG_LCLA,
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D40_DREG_PRMSE,
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D40_DREG_PRMSO,
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D40_DREG_PRMOE,
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D40_DREG_PRMOO,
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};
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#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
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/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
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static u32 d40_backup_regs_v3[] = {
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D40_DREG_PSEG1,
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D40_DREG_PSEG2,
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D40_DREG_PSEG3,
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D40_DREG_PSEG4,
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D40_DREG_PCEG1,
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D40_DREG_PCEG2,
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D40_DREG_PCEG3,
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D40_DREG_PCEG4,
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D40_DREG_RSEG1,
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D40_DREG_RSEG2,
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D40_DREG_RSEG3,
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D40_DREG_RSEG4,
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D40_DREG_RCEG1,
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D40_DREG_RCEG2,
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D40_DREG_RCEG3,
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D40_DREG_RCEG4,
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};
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#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
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static u32 d40_backup_regs_chan[] = {
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D40_CHAN_REG_SSCFG,
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D40_CHAN_REG_SSELT,
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D40_CHAN_REG_SSPTR,
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D40_CHAN_REG_SSLNK,
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D40_CHAN_REG_SDCFG,
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D40_CHAN_REG_SDELT,
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D40_CHAN_REG_SDPTR,
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D40_CHAN_REG_SDLNK,
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};
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/**
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* struct d40_lli_pool - Structure for keeping LLIs in memory
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*
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@ -96,7 +150,7 @@ struct d40_lli_pool {
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* during a transfer.
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* @node: List entry.
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* @is_in_client_list: true if the client owns this descriptor.
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* the previous one.
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* @cyclic: true if this is a cyclic job
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*
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* This descriptor is used for both logical and physical transfers.
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*/
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@ -143,6 +197,7 @@ struct d40_lcla_pool {
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* channels.
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*
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* @lock: A lock protection this entity.
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* @reserved: True if used by secure world or otherwise.
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* @num: The physical channel number of this entity.
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* @allocated_src: Bit mapped to show which src event line's are mapped to
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* this physical channel. Can also be free or physically allocated.
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@ -152,6 +207,7 @@ struct d40_lcla_pool {
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*/
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struct d40_phy_res {
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spinlock_t lock;
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bool reserved;
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int num;
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u32 allocated_src;
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u32 allocated_dst;
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@ -185,7 +241,6 @@ struct d40_base;
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* @src_def_cfg: Default cfg register setting for src.
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* @dst_def_cfg: Default cfg register setting for dst.
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* @log_def: Default logical channel settings.
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* @lcla: Space for one dst src pair for logical channel transfers.
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* @lcpa: Pointer to dst and src lcpa settings.
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* @runtime_addr: runtime configured address.
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* @runtime_direction: runtime configured direction.
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@ -241,6 +296,7 @@ struct d40_chan {
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* @dma_both: dma_device channels that can do both memcpy and slave transfers.
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* @dma_slave: dma_device channels that can do only do slave transfers.
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* @dma_memcpy: dma_device channels that can do only do memcpy transfers.
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* @phy_chans: Room for all possible physical channels in system.
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* @log_chans: Room for all possible logical channels in system.
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* @lookup_log_chans: Used to map interrupt number to logical channel. Points
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* to log_chans entries.
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@ -254,6 +310,13 @@ struct d40_chan {
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* @phy_lcpa: The physical address of the LCPA.
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* @lcpa_size: The size of the LCPA area.
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* @desc_slab: cache for descriptors.
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* @reg_val_backup: Here the values of some hardware registers are stored
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* before the DMA is powered off. They are restored when the power is back on.
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* @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
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* later.
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* @reg_val_backup_chan: Backup data for standard channel parameter registers.
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* @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
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* @initialized: true if the dma has been initialized
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*/
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struct d40_base {
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spinlock_t interrupt_lock;
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@ -282,6 +345,11 @@ struct d40_base {
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dma_addr_t phy_lcpa;
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resource_size_t lcpa_size;
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struct kmem_cache *desc_slab;
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u32 reg_val_backup[BACKUP_REGS_SZ];
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u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3];
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u32 *reg_val_backup_chan;
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u16 gcc_pwr_off_mask;
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bool initialized;
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};
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/**
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@ -479,13 +547,14 @@ static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
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struct d40_desc *d;
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struct d40_desc *_d;
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list_for_each_entry_safe(d, _d, &d40c->client, node)
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list_for_each_entry_safe(d, _d, &d40c->client, node) {
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if (async_tx_test_ack(&d->txd)) {
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d40_desc_remove(d);
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desc = d;
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memset(desc, 0, sizeof(*desc));
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break;
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}
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}
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}
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if (!desc)
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@ -740,7 +809,61 @@ static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
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return len;
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}
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/* Support functions for logical channels */
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#ifdef CONFIG_PM
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static void dma40_backup(void __iomem *baseaddr, u32 *backup,
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u32 *regaddr, int num, bool save)
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{
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int i;
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for (i = 0; i < num; i++) {
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void __iomem *addr = baseaddr + regaddr[i];
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if (save)
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backup[i] = readl_relaxed(addr);
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else
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writel_relaxed(backup[i], addr);
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}
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}
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static void d40_save_restore_registers(struct d40_base *base, bool save)
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{
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int i;
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/* Save/Restore channel specific registers */
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for (i = 0; i < base->num_phy_chans; i++) {
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void __iomem *addr;
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int idx;
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if (base->phy_res[i].reserved)
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continue;
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addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
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idx = i * ARRAY_SIZE(d40_backup_regs_chan);
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dma40_backup(addr, &base->reg_val_backup_chan[idx],
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d40_backup_regs_chan,
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ARRAY_SIZE(d40_backup_regs_chan),
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save);
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}
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/* Save/Restore global registers */
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dma40_backup(base->virtbase, base->reg_val_backup,
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d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
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save);
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/* Save/Restore registers only existing on dma40 v3 and later */
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if (base->rev >= 3)
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dma40_backup(base->virtbase, base->reg_val_backup_v3,
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d40_backup_regs_v3,
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ARRAY_SIZE(d40_backup_regs_v3),
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save);
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}
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#else
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static void d40_save_restore_registers(struct d40_base *base, bool save)
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{
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}
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#endif
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static int d40_channel_execute_command(struct d40_chan *d40c,
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enum d40_command command)
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@ -1013,6 +1136,7 @@ static int d40_pause(struct d40_chan *d40c)
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if (!d40c->busy)
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return 0;
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pm_runtime_get_sync(d40c->base->dev);
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spin_lock_irqsave(&d40c->lock, flags);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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@ -1025,7 +1149,8 @@ static int d40_pause(struct d40_chan *d40c)
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D40_DMA_RUN);
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}
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}
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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@ -1039,7 +1164,7 @@ static int d40_resume(struct d40_chan *d40c)
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return 0;
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spin_lock_irqsave(&d40c->lock, flags);
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pm_runtime_get_sync(d40c->base->dev);
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if (d40c->base->rev == 0)
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if (chan_is_logical(d40c)) {
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res = d40_channel_execute_command(d40c,
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@ -1057,6 +1182,8 @@ static int d40_resume(struct d40_chan *d40c)
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}
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no_suspend:
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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@ -1129,7 +1256,10 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
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d40d = d40_first_queued(d40c);
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if (d40d != NULL) {
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d40c->busy = true;
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if (!d40c->busy)
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d40c->busy = true;
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pm_runtime_get_sync(d40c->base->dev);
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/* Remove from queue */
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d40_desc_remove(d40d);
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@ -1190,6 +1320,8 @@ static void dma_tc_handle(struct d40_chan *d40c)
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if (d40_queue_start(d40c) == NULL)
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d40c->busy = false;
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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}
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d40c->pending_tx++;
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@ -1643,10 +1775,11 @@ static int d40_free_dma(struct d40_chan *d40c)
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return -EINVAL;
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}
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pm_runtime_get_sync(d40c->base->dev);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res) {
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chan_err(d40c, "suspend failed\n");
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return res;
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goto out;
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}
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if (chan_is_logical(d40c)) {
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@ -1664,13 +1797,11 @@ static int d40_free_dma(struct d40_chan *d40c)
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if (d40_chan_has_events(d40c)) {
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res = d40_channel_execute_command(d40c,
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D40_DMA_RUN);
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if (res) {
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if (res)
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chan_err(d40c,
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"Executing RUN command\n");
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return res;
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}
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}
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return 0;
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goto out;
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}
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} else {
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(void) d40_alloc_mask_free(phy, is_src, 0);
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@ -1680,13 +1811,23 @@ static int d40_free_dma(struct d40_chan *d40c)
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res = d40_channel_execute_command(d40c, D40_DMA_STOP);
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if (res) {
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chan_err(d40c, "Failed to stop channel\n");
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return res;
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goto out;
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}
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if (d40c->busy) {
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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}
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d40c->busy = false;
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d40c->phy_chan = NULL;
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d40c->configured = false;
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d40c->base->lookup_phy_chans[phy->num] = NULL;
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out:
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return 0;
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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return res;
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}
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static bool d40_is_paused(struct d40_chan *d40c)
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@ -2016,9 +2157,11 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
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err = d40_allocate_channel(d40c);
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if (err) {
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chan_err(d40c, "Failed to allocate channel\n");
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d40c->configured = false;
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goto fail;
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}
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pm_runtime_get_sync(d40c->base->dev);
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/* Fill in basic CFG register values */
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d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
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&d40c->dst_def_cfg, chan_is_logical(d40c));
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@ -2046,6 +2189,8 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
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if (is_free_phy)
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d40_config_write(d40c);
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fail:
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return err;
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}
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@ -2519,6 +2664,55 @@ static int __init d40_dmaengine_init(struct d40_base *base,
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return err;
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}
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/* Suspend resume functionality */
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#ifdef CONFIG_PM
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static int dma40_pm_suspend(struct device *dev)
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{
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if (!pm_runtime_suspended(dev))
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return -EBUSY;
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return 0;
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}
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static int dma40_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct d40_base *base = platform_get_drvdata(pdev);
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d40_save_restore_registers(base, true);
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/* Don't disable/enable clocks for v1 due to HW bugs */
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if (base->rev != 1)
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writel_relaxed(base->gcc_pwr_off_mask,
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base->virtbase + D40_DREG_GCC);
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return 0;
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}
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static int dma40_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct d40_base *base = platform_get_drvdata(pdev);
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if (base->initialized)
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d40_save_restore_registers(base, false);
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writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
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base->virtbase + D40_DREG_GCC);
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return 0;
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}
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static const struct dev_pm_ops dma40_pm_ops = {
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.suspend = dma40_pm_suspend,
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.runtime_suspend = dma40_runtime_suspend,
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.runtime_resume = dma40_runtime_resume,
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};
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#define DMA40_PM_OPS (&dma40_pm_ops)
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#else
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#define DMA40_PM_OPS NULL
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#endif
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/* Initialization functions. */
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static int __init d40_phy_res_init(struct d40_base *base)
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@ -2527,6 +2721,7 @@ static int __init d40_phy_res_init(struct d40_base *base)
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int num_phy_chans_avail = 0;
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u32 val[2];
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int odd_even_bit = -2;
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int gcc = D40_DREG_GCC_ENA;
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val[0] = readl(base->virtbase + D40_DREG_PRSME);
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val[1] = readl(base->virtbase + D40_DREG_PRSMO);
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@ -2538,9 +2733,17 @@ static int __init d40_phy_res_init(struct d40_base *base)
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/* Mark security only channels as occupied */
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base->phy_res[i].allocated_src = D40_ALLOC_PHY;
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base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
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base->phy_res[i].reserved = true;
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gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
|
||||
D40_DREG_GCC_SRC);
|
||||
gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
|
||||
D40_DREG_GCC_DST);
|
||||
|
||||
|
||||
} else {
|
||||
base->phy_res[i].allocated_src = D40_ALLOC_FREE;
|
||||
base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
|
||||
base->phy_res[i].reserved = false;
|
||||
num_phy_chans_avail++;
|
||||
}
|
||||
spin_lock_init(&base->phy_res[i].lock);
|
||||
|
|
@ -2552,6 +2755,11 @@ static int __init d40_phy_res_init(struct d40_base *base)
|
|||
|
||||
base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
|
||||
base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
|
||||
base->phy_res[chan].reserved = true;
|
||||
gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
|
||||
D40_DREG_GCC_SRC);
|
||||
gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
|
||||
D40_DREG_GCC_DST);
|
||||
num_phy_chans_avail--;
|
||||
}
|
||||
|
||||
|
|
@ -2572,6 +2780,15 @@ static int __init d40_phy_res_init(struct d40_base *base)
|
|||
val[0] = val[0] >> 2;
|
||||
}
|
||||
|
||||
/*
|
||||
* To keep things simple, Enable all clocks initially.
|
||||
* The clocks will get managed later post channel allocation.
|
||||
* The clocks for the event lines on which reserved channels exists
|
||||
* are not managed here.
|
||||
*/
|
||||
writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
|
||||
base->gcc_pwr_off_mask = gcc;
|
||||
|
||||
return num_phy_chans_avail;
|
||||
}
|
||||
|
||||
|
|
@ -2699,10 +2916,15 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
|
|||
goto failure;
|
||||
}
|
||||
|
||||
base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
|
||||
sizeof(struct d40_desc *) *
|
||||
D40_LCLA_LINK_PER_EVENT_GRP,
|
||||
base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
|
||||
sizeof(d40_backup_regs_chan),
|
||||
GFP_KERNEL);
|
||||
if (!base->reg_val_backup_chan)
|
||||
goto failure;
|
||||
|
||||
base->lcla_pool.alloc_map =
|
||||
kzalloc(num_phy_chans * sizeof(struct d40_desc *)
|
||||
* D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
|
||||
if (!base->lcla_pool.alloc_map)
|
||||
goto failure;
|
||||
|
||||
|
|
@ -2741,9 +2963,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
|
|||
static void __init d40_hw_init(struct d40_base *base)
|
||||
{
|
||||
|
||||
static const struct d40_reg_val dma_init_reg[] = {
|
||||
static struct d40_reg_val dma_init_reg[] = {
|
||||
/* Clock every part of the DMA block from start */
|
||||
{ .reg = D40_DREG_GCC, .val = 0x0000ff01},
|
||||
{ .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
|
||||
|
||||
/* Interrupts on all logical channels */
|
||||
{ .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
|
||||
|
|
@ -2960,6 +3182,12 @@ static int __init d40_probe(struct platform_device *pdev)
|
|||
goto failure;
|
||||
}
|
||||
|
||||
pm_runtime_irq_safe(base->dev);
|
||||
pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
|
||||
pm_runtime_use_autosuspend(base->dev);
|
||||
pm_runtime_enable(base->dev);
|
||||
pm_runtime_resume(base->dev);
|
||||
base->initialized = true;
|
||||
err = d40_dmaengine_init(base, num_reserved_chans);
|
||||
if (err)
|
||||
goto failure;
|
||||
|
|
@ -3013,6 +3241,7 @@ static struct platform_driver d40_driver = {
|
|||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = D40_NAME,
|
||||
.pm = DMA40_PM_OPS,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
|
||||
#define D40_TYPE_TO_GROUP(type) (type / 16)
|
||||
#define D40_TYPE_TO_EVENT(type) (type % 16)
|
||||
#define D40_GROUP_SIZE 8
|
||||
#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
|
||||
|
||||
/* Most bits of the CFG register are the same in log as in phy mode */
|
||||
#define D40_SREG_CFG_MST_POS 15
|
||||
|
|
@ -123,6 +125,15 @@
|
|||
|
||||
/* DMA Register Offsets */
|
||||
#define D40_DREG_GCC 0x000
|
||||
#define D40_DREG_GCC_ENA 0x1
|
||||
/* This assumes that there are only 4 event groups */
|
||||
#define D40_DREG_GCC_ENABLE_ALL 0xff01
|
||||
#define D40_DREG_GCC_EVTGRP_POS 8
|
||||
#define D40_DREG_GCC_SRC 0
|
||||
#define D40_DREG_GCC_DST 1
|
||||
#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
|
||||
(1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
|
||||
|
||||
#define D40_DREG_PRTYP 0x004
|
||||
#define D40_DREG_PRSME 0x008
|
||||
#define D40_DREG_PRSMO 0x00C
|
||||
|
|
|
|||
Loading…
Reference in a new issue