[PATCH] skge: fix sparse warnings
Fix sparse warnings from using enum as part of arithmetic expression, and comment indentation fixes Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
e67bda55e2
commit
7f4b45c526
1 changed files with 73 additions and 73 deletions
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@ -389,10 +389,10 @@ enum {
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/* Packet Arbiter Registers */
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/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
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enum {
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PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
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PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
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PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
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PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
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PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
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PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
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PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
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PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
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PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
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PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
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PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
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@ -481,14 +481,14 @@ enum {
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/* RAM Buffer Register Offsets */
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enum {
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RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
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RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
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RB_END = 0x04,/* 32 bit RAM Buffer End Address */
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RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
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RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
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RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
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RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
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RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
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RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
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RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
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RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
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RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
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RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
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/* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
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RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
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RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
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@ -532,7 +532,7 @@ enum {
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PHY_ADDR_MARV = 0,
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};
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#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
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#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
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/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
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enum {
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@ -578,15 +578,15 @@ enum {
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MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
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MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
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MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
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#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
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MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
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};
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/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
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enum {
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MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
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/* Bit 14: reserved */
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MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
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MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
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MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
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MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
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MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
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MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
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MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
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@ -595,9 +595,10 @@ enum {
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MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
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MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
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MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
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MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
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};
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#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
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/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
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/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
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@ -1304,8 +1305,8 @@ enum {
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/* special defines for FIBER (88E1011S only) */
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enum {
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PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
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PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
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PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
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PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
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PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
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PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
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};
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@ -1320,7 +1321,7 @@ enum {
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/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
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enum {
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PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
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PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
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PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
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PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
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PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
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@ -1349,7 +1350,7 @@ enum {
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PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
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};
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#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
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#define PHY_M_PC_MDI_XMODE(x) ((((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
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enum {
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PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
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@ -1432,24 +1433,24 @@ enum {
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PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
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PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
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/* (88E1011 only) */
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PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
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PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
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/* (88E1011 only) */
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PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
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PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
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/* (88E1111 only) */
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PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
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PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
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/* !!! Errata in spec. (1 = disable) */
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PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
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PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
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PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
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PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
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PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
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PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
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PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
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PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
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PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
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PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
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PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
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PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
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#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
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#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
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#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
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#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
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#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
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#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
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#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
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#define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
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/* 100=5x; 101=6x; 110=7x; 111=8x */
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enum {
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MAC_TX_CLK_0_MHZ = 2,
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@ -1468,10 +1469,12 @@ enum {
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PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
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/* (88E1111 only) */
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};
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#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
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#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
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enum {
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PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
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/* (88E1011 only) */
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PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
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/* (88E1011 only) */
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PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
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PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
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PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
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@ -1479,27 +1482,24 @@ enum {
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PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
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};
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#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
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enum {
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PULS_NO_STR = 0,/* no pulse stretching */
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PULS_21MS = 1,/* 21 ms to 42 ms */
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PULS_42MS = 2,/* 42 ms to 84 ms */
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PULS_84MS = 3,/* 84 ms to 170 ms */
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PULS_170MS = 4,/* 170 ms to 340 ms */
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PULS_340MS = 5,/* 340 ms to 670 ms */
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PULS_670MS = 6,/* 670 ms to 1.3 s */
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PULS_1300MS = 7,/* 1.3 s to 2.7 s */
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PULS_NO_STR = 0, /* no pulse stretching */
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PULS_21MS = 1, /* 21 ms to 42 ms */
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PULS_42MS = 2, /* 42 ms to 84 ms */
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PULS_84MS = 3, /* 84 ms to 170 ms */
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PULS_170MS = 4, /* 170 ms to 340 ms */
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PULS_340MS = 5, /* 340 ms to 670 ms */
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PULS_670MS = 6, /* 670 ms to 1.3 s */
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PULS_1300MS = 7, /* 1.3 s to 2.7 s */
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};
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#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
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enum {
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BLINK_42MS = 0,/* 42 ms */
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BLINK_84MS = 1,/* 84 ms */
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BLINK_170MS = 2,/* 170 ms */
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BLINK_340MS = 3,/* 340 ms */
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BLINK_670MS = 4,/* 670 ms */
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BLINK_42MS = 0, /* 42 ms */
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BLINK_84MS = 1, /* 84 ms */
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BLINK_170MS = 2, /* 170 ms */
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BLINK_340MS = 3, /* 340 ms */
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BLINK_670MS = 4, /* 670 ms */
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};
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/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
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@ -1525,7 +1525,7 @@ enum {
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PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
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PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
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PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
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PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
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PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
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};
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/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
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@ -1550,7 +1550,7 @@ enum {
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PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
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/* (88E1111 only) */
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PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
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PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
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PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
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/* (88E1111 only) */
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PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
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};
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@ -1605,9 +1605,9 @@ enum {
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/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
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enum {
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PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
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PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
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PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
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PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
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PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
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PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
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};
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@ -1804,8 +1804,8 @@ enum {
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/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
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enum {
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GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
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GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
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GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
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GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
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GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
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GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
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GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
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@ -1875,9 +1875,9 @@ enum {
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/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
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enum {
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GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
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GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
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GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
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GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
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GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
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GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
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GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
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GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
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@ -2111,18 +2111,18 @@ enum {
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/* XM_MMU_CMD 16 bit r/w MMU Command Register */
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enum {
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XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */
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XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */
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XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */
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XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
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XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
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XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
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XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
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XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
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XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
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XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
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XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
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XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
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XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
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XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
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XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
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XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
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XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
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XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
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XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
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XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
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XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
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XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
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XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
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XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
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};
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@ -2506,7 +2506,7 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
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}
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/* MAC Related Registers inside the device. */
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#define SK_REG(port,reg) (((port)<<7)+(reg))
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#define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
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#define SK_XMAC_REG(port, reg) \
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((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
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