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Blackfin arch: do not muck with the UART during boot -- let the serial driver worry about it

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Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger 2008-08-14 15:15:43 +08:00 committed by Bryan Wu
parent 95a86b5e51
commit 7e1e7aed0c
6 changed files with 0 additions and 183 deletions
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36
arch/blackfin/mach-bf527/head.S
View file

@ -35,42 +35,6 @@
#include <asm/mach/mem_init.h>
#endif
.extern _bf53x_relocate_l1_mem
__INIT
ENTRY(_mach_early_start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
p0.h = hi(UART1_LCR);
p0.l = lo(UART1_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
p0.h = hi(UART1_DLL);
p0.l = lo(UART1_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(UART1_DLH);
p0.l = lo(UART1_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(UART1_GCTL);
p0.l = lo(UART1_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
rts;
ENDPROC(_mach_early_start)
__FINIT
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)

48
arch/blackfin/mach-bf533/head.S
View file

@ -35,54 +35,6 @@
#include <asm/mach/mem_init.h>
#endif
.extern _bf53x_relocate_l1_mem
__INIT
ENTRY(_mach_early_start)
p0.h = hi(FIO_MASKA_C);
p0.l = lo(FIO_MASKA_C);
r0 = 0xFFFF(Z);
w[p0] = r0.L; /* Disable all interrupts */
ssync;
p0.h = hi(FIO_MASKB_C);
p0.l = lo(FIO_MASKB_C);
r0 = 0xFFFF(Z);
w[p0] = r0.L; /* Disable all interrupts */
ssync;
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
p0.h = hi(BFIN_UART_LCR);
p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
p0.h = hi(BFIN_UART_DLL);
p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_DLH);
p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
rts;
ENDPROC(_mach_early_start)
__FINIT
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)

50
arch/blackfin/mach-bf537/head.S
View file

@ -35,56 +35,6 @@
#include <asm/mach/mem_init.h>
#endif
.extern _bf53x_relocate_l1_mem
__INIT
ENTRY(_mach_early_start)
/* Initialise General-Purpose I/O Modules on BF537 */
p0.h = hi(BFIN_PORT_MUX);
p0.l = lo(BFIN_PORT_MUX);
R0 = (PGDE_UART | PFTE_UART)(Z);
W[P0] = R0.L; /* Enable both UARTS */
SSYNC;
/* Enable peripheral function of PORTF for UART0 and UART1 */
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
R0 = 0x000F(Z);
W[P0] = R0.L;
SSYNC;
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
p0.h = hi(BFIN_UART_LCR);
p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
p0.h = hi(BFIN_UART_DLL);
p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_DLH);
p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
rts;
ENDPROC(_mach_early_start)
__FINIT
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)

10
arch/blackfin/mach-bf548/head.S
View file

@ -35,16 +35,6 @@
#include <asm/mach/mem_init.h>
#endif
.extern _bf53x_relocate_l1_mem
__INIT
ENTRY(_mach_early_start)
rts;
ENDPROC(_mach_early_start)
__FINIT
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)

36
arch/blackfin/mach-bf561/head.S
View file

@ -35,42 +35,6 @@
#include <asm/mach/mem_init.h>
#endif
.extern _bf53x_relocate_l1_mem
__INIT
ENTRY(_mach_early_start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
p0.h = hi(BFIN_UART_LCR);
p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
p0.h = hi(BFIN_UART_DLL);
p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_DLH);
p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
rts;
ENDPROC(_mach_early_start)
__FINIT
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)

3
arch/blackfin/mach-common/head.S
View file

@ -96,9 +96,6 @@ ENTRY(__start)
R0 = RETX;
[P0] = R0;
/* Let each Blackfin family do its own thing */
call _mach_early_start;
/* Initialize stack pointer */
sp.l = lo(INITIAL_STACK);
sp.h = hi(INITIAL_STACK);