[S390] rename lowcore field
The 16 bit value at the lowcore location with offset 0x84 is the cpu address that is associated with an external interrupt. Rename the field from cpu_addr to ext_cpu_addr to make that clear. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
parent
4fdf7f432c
commit
7e180bd802
6 changed files with 10 additions and 10 deletions
|
@ -56,7 +56,7 @@ struct _lowcore {
|
||||||
psw_t mcck_new_psw; /* 0x0070 */
|
psw_t mcck_new_psw; /* 0x0070 */
|
||||||
psw_t io_new_psw; /* 0x0078 */
|
psw_t io_new_psw; /* 0x0078 */
|
||||||
__u32 ext_params; /* 0x0080 */
|
__u32 ext_params; /* 0x0080 */
|
||||||
__u16 cpu_addr; /* 0x0084 */
|
__u16 ext_cpu_addr; /* 0x0084 */
|
||||||
__u16 ext_int_code; /* 0x0086 */
|
__u16 ext_int_code; /* 0x0086 */
|
||||||
__u16 svc_ilc; /* 0x0088 */
|
__u16 svc_ilc; /* 0x0088 */
|
||||||
__u16 svc_code; /* 0x008a */
|
__u16 svc_code; /* 0x008a */
|
||||||
|
@ -189,7 +189,7 @@ struct _lowcore {
|
||||||
__u32 ipl_parmblock_ptr; /* 0x0014 */
|
__u32 ipl_parmblock_ptr; /* 0x0014 */
|
||||||
__u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
|
__u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
|
||||||
__u32 ext_params; /* 0x0080 */
|
__u32 ext_params; /* 0x0080 */
|
||||||
__u16 cpu_addr; /* 0x0084 */
|
__u16 ext_cpu_addr; /* 0x0084 */
|
||||||
__u16 ext_int_code; /* 0x0086 */
|
__u16 ext_int_code; /* 0x0086 */
|
||||||
__u16 svc_ilc; /* 0x0088 */
|
__u16 svc_ilc; /* 0x0088 */
|
||||||
__u16 svc_code; /* 0x008a */
|
__u16 svc_code; /* 0x008a */
|
||||||
|
|
|
@ -78,7 +78,7 @@ int main(void)
|
||||||
BLANK();
|
BLANK();
|
||||||
/* lowcore offsets */
|
/* lowcore offsets */
|
||||||
DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
|
DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
|
||||||
DEFINE(__LC_CPU_ADDRESS, offsetof(struct _lowcore, cpu_addr));
|
DEFINE(__LC_EXT_CPU_ADDR, offsetof(struct _lowcore, ext_cpu_addr));
|
||||||
DEFINE(__LC_EXT_INT_CODE, offsetof(struct _lowcore, ext_int_code));
|
DEFINE(__LC_EXT_INT_CODE, offsetof(struct _lowcore, ext_int_code));
|
||||||
DEFINE(__LC_SVC_ILC, offsetof(struct _lowcore, svc_ilc));
|
DEFINE(__LC_SVC_ILC, offsetof(struct _lowcore, svc_ilc));
|
||||||
DEFINE(__LC_SVC_INT_CODE, offsetof(struct _lowcore, svc_code));
|
DEFINE(__LC_SVC_INT_CODE, offsetof(struct _lowcore, svc_code));
|
||||||
|
|
|
@ -606,7 +606,7 @@ ext_skip:
|
||||||
stm %r8,%r9,__PT_PSW(%r11)
|
stm %r8,%r9,__PT_PSW(%r11)
|
||||||
TRACE_IRQS_OFF
|
TRACE_IRQS_OFF
|
||||||
lr %r2,%r11 # pass pointer to pt_regs
|
lr %r2,%r11 # pass pointer to pt_regs
|
||||||
l %r3,__LC_CPU_ADDRESS # get cpu address + interruption code
|
l %r3,__LC_EXT_CPU_ADDR # get cpu address + interruption code
|
||||||
l %r4,__LC_EXT_PARAMS # get external parameters
|
l %r4,__LC_EXT_PARAMS # get external parameters
|
||||||
l %r1,BASED(.Ldo_extint)
|
l %r1,BASED(.Ldo_extint)
|
||||||
basr %r14,%r1 # call do_extint
|
basr %r14,%r1 # call do_extint
|
||||||
|
|
|
@ -625,7 +625,7 @@ ext_skip:
|
||||||
TRACE_IRQS_OFF
|
TRACE_IRQS_OFF
|
||||||
lghi %r1,4096
|
lghi %r1,4096
|
||||||
lgr %r2,%r11 # pass pointer to pt_regs
|
lgr %r2,%r11 # pass pointer to pt_regs
|
||||||
llgf %r3,__LC_CPU_ADDRESS # get cpu address + interruption code
|
llgf %r3,__LC_EXT_CPU_ADDR # get cpu address + interruption code
|
||||||
llgf %r4,__LC_EXT_PARAMS # get external parameter
|
llgf %r4,__LC_EXT_PARAMS # get external parameter
|
||||||
lg %r5,__LC_EXT_PARAMS2-4096(%r1) # get 64 bit external parameter
|
lg %r5,__LC_EXT_PARAMS2-4096(%r1) # get 64 bit external parameter
|
||||||
brasl %r14,do_extint
|
brasl %r14,do_extint
|
||||||
|
|
|
@ -42,7 +42,7 @@ ENTRY(swsusp_arch_suspend)
|
||||||
lghi %r1,0x1000
|
lghi %r1,0x1000
|
||||||
|
|
||||||
/* Save CPU address */
|
/* Save CPU address */
|
||||||
stap __LC_CPU_ADDRESS(%r0)
|
stap __LC_EXT_CPU_ADDR(%r0)
|
||||||
|
|
||||||
/* Store registers */
|
/* Store registers */
|
||||||
mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
|
mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
|
||||||
|
@ -173,7 +173,7 @@ pgm_check_entry:
|
||||||
larl %r1,.Lresume_cpu /* Resume CPU address: r2 */
|
larl %r1,.Lresume_cpu /* Resume CPU address: r2 */
|
||||||
stap 0(%r1)
|
stap 0(%r1)
|
||||||
llgh %r2,0(%r1)
|
llgh %r2,0(%r1)
|
||||||
llgh %r1,__LC_CPU_ADDRESS(%r0) /* Suspend CPU address: r1 */
|
llgh %r1,__LC_EXT_CPU_ADDR(%r0) /* Suspend CPU address: r1 */
|
||||||
cgr %r1,%r2
|
cgr %r1,%r2
|
||||||
je restore_registers /* r1 = r2 -> nothing to do */
|
je restore_registers /* r1 = r2 -> nothing to do */
|
||||||
larl %r4,.Lrestart_suspend_psw /* Set new restart PSW */
|
larl %r4,.Lrestart_suspend_psw /* Set new restart PSW */
|
||||||
|
|
|
@ -134,7 +134,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, inti->emerg.code);
|
rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->emerg.code);
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
|
@ -156,7 +156,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, inti->extcall.code);
|
rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->extcall.code);
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
|
@ -202,7 +202,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, 0x0d00);
|
rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, 0x0d00);
|
||||||
if (rc == -EFAULT)
|
if (rc == -EFAULT)
|
||||||
exception = 1;
|
exception = 1;
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue