i2c: rk3x: add i2c support for rk3399 soc
- new method to caculate i2c timings for rk3399: There was an timing issue about "repeated start" time at the I2C controller of version0, controller appears to drop SDA at .875x (7/8) programmed clk high. On version 1 of the controller, the rule(.875x) isn't enough to meet tSU;STA requirements on 100k's Standard-mode. To resolve this issue, sda_update_config, start_setup_config and stop_setup_config for I2C timing information are added, new rules are designed to calculate the timing information at new v1. - pclk and function clk are separated at rk3399 Signed-off-by: David Wu <david.wu@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> [wsa: fixed whitespace issue] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
David Wu
Wolfram Sang
parent
908dbd5391
commit
7e086c3fc2
1 changed files with 274 additions and 20 deletions
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@ -58,6 +58,12 @@ enum {
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#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
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#define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
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#define REG_CON_TUNING_MASK GENMASK(15, 8)
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#define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
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#define REG_CON_STA_CFG(cfg) ((cfg) << 12)
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#define REG_CON_STO_CFG(cfg) ((cfg) << 14)
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/* REG_MRXADDR bits */
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#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
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@ -77,40 +83,62 @@ enum {
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/**
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* struct i2c_spec_values:
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* @min_hold_start_ns: min hold time (repeated) START condition
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* @min_low_ns: min LOW period of the SCL clock
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* @min_high_ns: min HIGH period of the SCL cloc
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* @min_setup_start_ns: min set-up time for a repeated START conditio
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* @max_data_hold_ns: max data hold time
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* @min_data_setup_ns: min data set-up time
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* @min_setup_stop_ns: min set-up time for STOP condition
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* @min_hold_buffer_ns: min bus free time between a STOP and
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* START condition
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*/
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struct i2c_spec_values {
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unsigned long min_hold_start_ns;
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unsigned long min_low_ns;
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unsigned long min_high_ns;
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unsigned long min_setup_start_ns;
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unsigned long max_data_hold_ns;
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unsigned long min_data_setup_ns;
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unsigned long min_setup_stop_ns;
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unsigned long min_hold_buffer_ns;
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};
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static const struct i2c_spec_values standard_mode_spec = {
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.min_hold_start_ns = 4000,
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.min_low_ns = 4700,
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.min_high_ns = 4000,
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.min_setup_start_ns = 4700,
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.max_data_hold_ns = 3450,
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.min_data_setup_ns = 250,
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.min_setup_stop_ns = 4000,
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.min_hold_buffer_ns = 4700,
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};
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static const struct i2c_spec_values fast_mode_spec = {
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.min_hold_start_ns = 600,
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.min_low_ns = 1300,
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.min_high_ns = 600,
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.min_setup_start_ns = 600,
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.max_data_hold_ns = 900,
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.min_data_setup_ns = 100,
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.min_setup_stop_ns = 600,
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.min_hold_buffer_ns = 1300,
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};
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/**
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* struct rk3x_i2c_calced_timings:
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* @div_low: Divider output for low
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* @div_high: Divider output for high
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* @tuning: Used to adjust setup/hold data time,
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* setup/hold start time and setup stop time for
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* v1's calc_timings, the tuning should all be 0
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* for old hardware anyone using v0's calc_timings.
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*/
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struct rk3x_i2c_calced_timings {
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unsigned long div_low;
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unsigned long div_high;
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unsigned int tuning;
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};
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enum rk3x_i2c_state {
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@ -123,9 +151,12 @@ enum rk3x_i2c_state {
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/**
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* @grf_offset: offset inside the grf regmap for setting the i2c type
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* @calc_timings: Callback function for i2c timing information calculated
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*/
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struct rk3x_i2c_soc_data {
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int grf_offset;
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int (*calc_timings)(unsigned long, struct i2c_timings *,
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struct rk3x_i2c_calced_timings *);
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};
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/**
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@ -134,7 +165,8 @@ struct rk3x_i2c_soc_data {
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* @dev: device for this controller
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* @soc_data: related soc data struct
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* @regs: virtual memory area
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* @clk: clock of i2c bus
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* @clk: function clk for rk3399 or function & Bus clks for others
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* @pclk: Bus clk for rk3399
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* @clk_rate_nb: i2c clk rate change notify
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* @t: I2C known timing information
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* @lock: spinlock for the i2c bus
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@ -156,6 +188,7 @@ struct rk3x_i2c {
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/* Hardware resources */
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void __iomem *regs;
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struct clk *clk;
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struct clk *pclk;
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struct notifier_block clk_rate_nb;
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/* Settings */
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@ -200,12 +233,12 @@ static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
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*/
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static void rk3x_i2c_start(struct rk3x_i2c *i2c)
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{
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u32 val;
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u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
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i2c_writel(i2c, REG_INT_START, REG_IEN);
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/* enable adapter with correct mode, send START condition */
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val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
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val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
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/* if we want to react to NACK, set ACTACK bit */
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if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
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@ -246,7 +279,8 @@ static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
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* get the intended effect by resetting its internal state
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* and issuing an ordinary START.
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*/
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i2c_writel(i2c, 0, REG_CON);
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ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
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i2c_writel(i2c, ctrl, REG_CON);
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/* signal that we are finished with the current msg */
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wake_up(&i2c->wait);
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@ -513,9 +547,9 @@ static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
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* a best-effort divider value is returned in divs. If the target rate is
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* too high, we silently use the highest possible rate.
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*/
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static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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struct i2c_timings *t,
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struct rk3x_i2c_calced_timings *t_calc)
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static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
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struct i2c_timings *t,
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struct rk3x_i2c_calced_timings *t_calc)
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{
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unsigned long min_low_ns, min_high_ns;
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unsigned long max_low_ns, min_total_ns;
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@ -661,20 +695,191 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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return ret;
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}
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/**
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* Calculate timing values for desired SCL frequency
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*
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* @clk_rate: I2C input clock rate
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* @t: Known I2C timing information
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* @t_calc: Caculated rk3x private timings that would be written into regs
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*
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* Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
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* a best-effort divider value is returned in divs. If the target rate is
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* too high, we silently use the highest possible rate.
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* The following formulas are v1's method to calculate timings.
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*
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* l = divl + 1;
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* h = divh + 1;
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* s = sda_update_config + 1;
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* u = start_setup_config + 1;
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* p = stop_setup_config + 1;
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* T = Tclk_i2c;
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*
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* tHigh = 8 * h * T;
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* tLow = 8 * l * T;
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*
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* tHD;sda = (l * s + 1) * T;
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* tSU;sda = [(8 - s) * l + 1] * T;
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* tI2C = 8 * (l + h) * T;
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*
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* tSU;sta = (8h * u + 1) * T;
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* tHD;sta = [8h * (u + 1) - 1] * T;
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* tSU;sto = (8h * p + 1) * T;
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*/
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static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
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struct i2c_timings *t,
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struct rk3x_i2c_calced_timings *t_calc)
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{
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unsigned long min_low_ns, min_high_ns, min_total_ns;
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unsigned long min_setup_start_ns, min_setup_data_ns;
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unsigned long min_setup_stop_ns, max_hold_data_ns;
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unsigned long clk_rate_khz, scl_rate_khz;
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unsigned long min_low_div, min_high_div;
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unsigned long min_div_for_hold, min_total_div;
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unsigned long extra_div, extra_low_div;
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unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
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const struct i2c_spec_values *spec;
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int ret = 0;
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/* Support standard-mode and fast-mode */
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if (WARN_ON(t->bus_freq_hz > 400000))
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t->bus_freq_hz = 400000;
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/* prevent scl_rate_khz from becoming 0 */
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if (WARN_ON(t->bus_freq_hz < 1000))
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t->bus_freq_hz = 1000;
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/*
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* min_low_ns: The minimum number of ns we need to hold low to
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* meet I2C specification, should include fall time.
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* min_high_ns: The minimum number of ns we need to hold high to
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* meet I2C specification, should include rise time.
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*/
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spec = rk3x_i2c_get_spec(t->bus_freq_hz);
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/* calculate min-divh and min-divl */
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clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
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scl_rate_khz = t->bus_freq_hz / 1000;
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min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
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min_high_ns = t->scl_rise_ns + spec->min_high_ns;
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min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
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min_low_ns = t->scl_fall_ns + spec->min_low_ns;
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min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
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/*
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* Final divh and divl must be greater than 0, otherwise the
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* hardware would not output the i2c clk.
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*/
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min_high_div = (min_high_div < 1) ? 2 : min_high_div;
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min_low_div = (min_low_div < 1) ? 2 : min_low_div;
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/* These are the min dividers needed for min hold times. */
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min_div_for_hold = (min_low_div + min_high_div);
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min_total_ns = min_low_ns + min_high_ns;
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/*
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* This is the maximum divider so we don't go over the maximum.
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* We don't round up here (we round down) since this is a maximum.
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*/
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if (min_div_for_hold >= min_total_div) {
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/*
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* Time needed to meet hold requirements is important.
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* Just use that.
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*/
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t_calc->div_low = min_low_div;
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t_calc->div_high = min_high_div;
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} else {
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/*
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* We've got to distribute some time among the low and high
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* so we don't run too fast.
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* We'll try to split things up by the scale of min_low_div and
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* min_high_div, biasing slightly towards having a higher div
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* for low (spend more time low).
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*/
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extra_div = min_total_div - min_div_for_hold;
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extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
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min_div_for_hold);
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t_calc->div_low = min_low_div + extra_low_div;
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t_calc->div_high = min_high_div + (extra_div - extra_low_div);
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}
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/*
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* calculate sda data hold count by the rules, data_upd_st:3
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* is a appropriate value to reduce calculated times.
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*/
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for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
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max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
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* (t_calc->div_low) + 1)
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* 1000000, clk_rate_khz);
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min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
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* (t_calc->div_low) + 1)
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* 1000000, clk_rate_khz);
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if ((max_hold_data_ns < spec->max_data_hold_ns) &&
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(min_setup_data_ns > spec->min_data_setup_ns))
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break;
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}
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/* calculate setup start config */
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min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
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stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
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- 1000000, 8 * 1000000 * (t_calc->div_high));
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/* calculate setup stop config */
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min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
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stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
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- 1000000, 8 * 1000000 * (t_calc->div_high));
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t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
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REG_CON_STA_CFG(--stp_sta_cfg) |
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REG_CON_STO_CFG(--stp_sto_cfg);
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t_calc->div_low--;
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t_calc->div_high--;
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/* Maximum divider supported by hw is 0xffff */
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if (t_calc->div_low > 0xffff) {
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t_calc->div_low = 0xffff;
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ret = -EINVAL;
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}
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if (t_calc->div_high > 0xffff) {
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t_calc->div_high = 0xffff;
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ret = -EINVAL;
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}
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return ret;
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}
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static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
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{
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struct i2c_timings *t = &i2c->t;
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struct rk3x_i2c_calced_timings calc;
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u64 t_low_ns, t_high_ns;
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unsigned long flags;
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u32 val;
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int ret;
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ret = rk3x_i2c_calc_divs(clk_rate, t, &calc);
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ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
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WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
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clk_enable(i2c->clk);
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clk_enable(i2c->pclk);
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spin_lock_irqsave(&i2c->lock, flags);
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val = i2c_readl(i2c, REG_CON);
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val &= ~REG_CON_TUNING_MASK;
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val |= calc.tuning;
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i2c_writel(i2c, val, REG_CON);
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i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
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REG_CLKDIV);
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clk_disable(i2c->clk);
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spin_unlock_irqrestore(&i2c->lock, flags);
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clk_disable(i2c->pclk);
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t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
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t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
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@ -712,7 +917,13 @@ static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
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switch (event) {
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case PRE_RATE_CHANGE:
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if (rk3x_i2c_calc_divs(ndata->new_rate, &i2c->t, &calc) != 0)
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/*
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* Try the calculation (but don't store the result) ahead of
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* time to see if we need to block the clock change. Timings
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* shouldn't actually take effect until rk3x_i2c_adapt_div().
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*/
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if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
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&calc) != 0)
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return NOTIFY_STOP;
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/* scale up */
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@ -822,12 +1033,14 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
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{
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struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
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unsigned long timeout, flags;
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u32 val;
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int ret = 0;
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int i;
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spin_lock_irqsave(&i2c->lock, flags);
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clk_enable(i2c->clk);
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clk_enable(i2c->pclk);
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i2c->is_last_msg = false;
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@ -861,7 +1074,9 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
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/* Force a STOP condition without interrupt */
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i2c_writel(i2c, 0, REG_IEN);
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i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON);
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val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
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val |= REG_CON_EN | REG_CON_STOP;
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i2c_writel(i2c, val, REG_CON);
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i2c->state = STATE_IDLE;
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@ -875,7 +1090,9 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
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}
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}
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clk_disable(i2c->pclk);
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clk_disable(i2c->clk);
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|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
|
||||
return ret < 0 ? ret : num;
|
||||
|
|
@ -893,18 +1110,27 @@ static const struct i2c_algorithm rk3x_i2c_algorithm = {
|
|||
|
||||
static const struct rk3x_i2c_soc_data rk3066_soc_data = {
|
||||
.grf_offset = 0x154,
|
||||
.calc_timings = rk3x_i2c_v0_calc_timings,
|
||||
};
|
||||
|
||||
static const struct rk3x_i2c_soc_data rk3188_soc_data = {
|
||||
.grf_offset = 0x0a4,
|
||||
.calc_timings = rk3x_i2c_v0_calc_timings,
|
||||
};
|
||||
|
||||
static const struct rk3x_i2c_soc_data rk3228_soc_data = {
|
||||
.grf_offset = -1,
|
||||
.calc_timings = rk3x_i2c_v0_calc_timings,
|
||||
};
|
||||
|
||||
static const struct rk3x_i2c_soc_data rk3288_soc_data = {
|
||||
.grf_offset = -1,
|
||||
.calc_timings = rk3x_i2c_v0_calc_timings,
|
||||
};
|
||||
|
||||
static const struct rk3x_i2c_soc_data rk3399_soc_data = {
|
||||
.grf_offset = -1,
|
||||
.calc_timings = rk3x_i2c_v1_calc_timings,
|
||||
};
|
||||
|
||||
static const struct of_device_id rk3x_i2c_match[] = {
|
||||
|
|
@ -924,6 +1150,10 @@ static const struct of_device_id rk3x_i2c_match[] = {
|
|||
.compatible = "rockchip,rk3288-i2c",
|
||||
.data = (void *)&rk3288_soc_data
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3399-i2c",
|
||||
.data = (void *)&rk3399_soc_data
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
|
||||
|
|
@ -963,12 +1193,6 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
|
|||
spin_lock_init(&i2c->lock);
|
||||
init_waitqueue_head(&i2c->wait);
|
||||
|
||||
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2c->clk)) {
|
||||
dev_err(&pdev->dev, "cannot get clock\n");
|
||||
return PTR_ERR(i2c->clk);
|
||||
}
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(i2c->regs))
|
||||
|
|
@ -1022,17 +1246,44 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, i2c);
|
||||
|
||||
if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
|
||||
/* Only one clock to use for bus clock and peripheral clock */
|
||||
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
i2c->pclk = i2c->clk;
|
||||
} else {
|
||||
i2c->clk = devm_clk_get(&pdev->dev, "i2c");
|
||||
i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
}
|
||||
|
||||
if (IS_ERR(i2c->clk)) {
|
||||
ret = PTR_ERR(i2c->clk);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
if (IS_ERR(i2c->pclk)) {
|
||||
ret = PTR_ERR(i2c->pclk);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare(i2c->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Could not prepare clock\n");
|
||||
dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ret = clk_prepare(i2c->pclk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
|
||||
ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "Unable to register clock notifier\n");
|
||||
goto err_clk;
|
||||
goto err_pclk;
|
||||
}
|
||||
|
||||
clk_rate = clk_get_rate(i2c->clk);
|
||||
|
|
@ -1050,6 +1301,8 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
err_clk_notifier:
|
||||
clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
|
||||
err_pclk:
|
||||
clk_unprepare(i2c->pclk);
|
||||
err_clk:
|
||||
clk_unprepare(i2c->clk);
|
||||
return ret;
|
||||
|
|
@ -1062,6 +1315,7 @@ static int rk3x_i2c_remove(struct platform_device *pdev)
|
|||
i2c_del_adapter(&i2c->adap);
|
||||
|
||||
clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
|
||||
clk_unprepare(i2c->pclk);
|
||||
clk_unprepare(i2c->clk);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in a new issue