crypto: atmel-sha - fix context switches
This patch saves the value of the internal hash register at the end of an 'update' operation then restores this value before starting the next 'update'. This way the driver can now properly handle context switches. WARNING: only hardware versions from sama5d4x and later provide the needed interface to update the internal hash value. Especially, sama5d3x cannot implement this feature so context switches are still broken. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Cyrille Pitchen
Herbert Xu
parent
507c5cc236
commit
7cee350816
2 changed files with 84 additions and 25 deletions
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@ -8,6 +8,8 @@
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#define SHA_CR_START (1 << 0)
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#define SHA_CR_FIRST (1 << 4)
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#define SHA_CR_SWRST (1 << 8)
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#define SHA_CR_WUIHV (1 << 12)
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#define SHA_CR_WUIEHV (1 << 13)
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#define SHA_MR 0x04
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#define SHA_MR_MODE_MASK (0x3 << 0)
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@ -15,6 +17,8 @@
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#define SHA_MR_MODE_AUTO 0x1
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#define SHA_MR_MODE_PDC 0x2
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#define SHA_MR_PROCDLY (1 << 4)
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#define SHA_MR_UIHV (1 << 5)
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#define SHA_MR_UIEHV (1 << 6)
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#define SHA_MR_ALGO_SHA1 (0 << 8)
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#define SHA_MR_ALGO_SHA256 (1 << 8)
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#define SHA_MR_ALGO_SHA384 (2 << 8)
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@ -53,6 +53,7 @@
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#define SHA_FLAGS_FINUP BIT(16)
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#define SHA_FLAGS_SG BIT(17)
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#define SHA_FLAGS_ALGO_MASK GENMASK(22, 18)
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#define SHA_FLAGS_SHA1 BIT(18)
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#define SHA_FLAGS_SHA224 BIT(19)
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#define SHA_FLAGS_SHA256 BIT(20)
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@ -60,6 +61,7 @@
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#define SHA_FLAGS_SHA512 BIT(22)
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#define SHA_FLAGS_ERROR BIT(23)
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#define SHA_FLAGS_PAD BIT(24)
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#define SHA_FLAGS_RESTORE BIT(25)
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#define SHA_OP_UPDATE 1
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#define SHA_OP_FINAL 2
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@ -73,6 +75,7 @@ struct atmel_sha_caps {
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bool has_dualbuff;
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bool has_sha224;
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bool has_sha_384_512;
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bool has_uihv;
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};
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struct atmel_sha_dev;
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@ -318,7 +321,8 @@ static int atmel_sha_init(struct ahash_request *req)
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static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
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{
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struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
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u32 valcr = 0, valmr = SHA_MR_MODE_AUTO;
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u32 valmr = SHA_MR_MODE_AUTO;
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unsigned int i, hashsize = 0;
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if (likely(dma)) {
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if (!dd->caps.has_dma)
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@ -330,22 +334,62 @@ static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
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atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
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}
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if (ctx->flags & SHA_FLAGS_SHA1)
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switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
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case SHA_FLAGS_SHA1:
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valmr |= SHA_MR_ALGO_SHA1;
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else if (ctx->flags & SHA_FLAGS_SHA224)
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hashsize = SHA1_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA224:
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valmr |= SHA_MR_ALGO_SHA224;
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else if (ctx->flags & SHA_FLAGS_SHA256)
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hashsize = SHA256_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA256:
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valmr |= SHA_MR_ALGO_SHA256;
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else if (ctx->flags & SHA_FLAGS_SHA384)
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hashsize = SHA256_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA384:
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valmr |= SHA_MR_ALGO_SHA384;
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else if (ctx->flags & SHA_FLAGS_SHA512)
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hashsize = SHA512_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA512:
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valmr |= SHA_MR_ALGO_SHA512;
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hashsize = SHA512_DIGEST_SIZE;
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break;
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default:
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break;
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}
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/* Setting CR_FIRST only for the first iteration */
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if (!(ctx->digcnt[0] || ctx->digcnt[1]))
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valcr = SHA_CR_FIRST;
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if (!(ctx->digcnt[0] || ctx->digcnt[1])) {
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atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
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} else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) {
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const u32 *hash = (const u32 *)ctx->digest;
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/*
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* Restore the hardware context: update the User Initialize
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* Hash Value (UIHV) with the value saved when the latest
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* 'update' operation completed on this very same crypto
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* request.
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*/
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ctx->flags &= ~SHA_FLAGS_RESTORE;
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atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
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for (i = 0; i < hashsize / sizeof(u32); ++i)
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atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]);
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atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
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valmr |= SHA_MR_UIHV;
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}
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/*
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* WARNING: If the UIHV feature is not available, the hardware CANNOT
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* process concurrent requests: the internal registers used to store
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* the hash/digest are still set to the partial digest output values
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* computed during the latest round.
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*/
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atmel_sha_write(dd, SHA_CR, valcr);
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atmel_sha_write(dd, SHA_MR, valmr);
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}
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@ -714,23 +758,31 @@ static void atmel_sha_copy_hash(struct ahash_request *req)
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{
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struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
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u32 *hash = (u32 *)ctx->digest;
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int i;
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unsigned int i, hashsize;
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if (ctx->flags & SHA_FLAGS_SHA1)
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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else if (ctx->flags & SHA_FLAGS_SHA224)
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for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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else if (ctx->flags & SHA_FLAGS_SHA256)
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for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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else if (ctx->flags & SHA_FLAGS_SHA384)
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for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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else
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for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
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case SHA_FLAGS_SHA1:
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hashsize = SHA1_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA224:
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case SHA_FLAGS_SHA256:
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hashsize = SHA256_DIGEST_SIZE;
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break;
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case SHA_FLAGS_SHA384:
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case SHA_FLAGS_SHA512:
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hashsize = SHA512_DIGEST_SIZE;
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break;
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default:
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/* Should not happen... */
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return;
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}
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for (i = 0; i < hashsize / sizeof(u32); ++i)
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hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
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ctx->flags |= SHA_FLAGS_RESTORE;
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}
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static void atmel_sha_copy_ready_hash(struct ahash_request *req)
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@ -1276,6 +1328,7 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
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dd->caps.has_dualbuff = 0;
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dd->caps.has_sha224 = 0;
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dd->caps.has_sha_384_512 = 0;
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dd->caps.has_uihv = 0;
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/* keep only major version number */
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switch (dd->hw_version & 0xff0) {
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@ -1284,12 +1337,14 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
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dd->caps.has_dualbuff = 1;
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dd->caps.has_sha224 = 1;
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dd->caps.has_sha_384_512 = 1;
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dd->caps.has_uihv = 1;
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break;
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case 0x420:
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dd->caps.has_dma = 1;
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dd->caps.has_dualbuff = 1;
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dd->caps.has_sha224 = 1;
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dd->caps.has_sha_384_512 = 1;
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dd->caps.has_uihv = 1;
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break;
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case 0x410:
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dd->caps.has_dma = 1;
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