[POWERPC] Clean up pci-bridge.h
No semantic changes. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Stephen Rothwell
Paul Mackerras
parent
96188ce57b
commit
7cd1de6bc1
1 changed files with 42 additions and 53 deletions
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@ -1,16 +1,17 @@
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#ifndef _ASM_POWERPC_PCI_BRIDGE_H
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#define _ASM_POWERPC_PCI_BRIDGE_H
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#ifdef __KERNEL__
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <linux/list.h>
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#include <linux/ioport.h>
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#ifndef CONFIG_PPC64
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struct device_node;
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struct pci_controller;
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/*
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* Structure of a PCI controller (host bridge)
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*/
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@ -51,11 +52,11 @@ struct pci_controller {
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* set.
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* BIG_ENDIAN - cfg_addr is a big endian register
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
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#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
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#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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@ -81,18 +82,18 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
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/* These are used for config access before all the PCI probing
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has been done. */
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int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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int where, u8 *val);
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int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
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int where, u16 *val);
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int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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int where, u32 *val);
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int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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int where, u8 val);
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int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
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int where, u16 val);
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int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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int where, u32 val);
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extern int early_read_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 *val);
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extern int early_read_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 *val);
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extern int early_read_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 *val);
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extern int early_write_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 val);
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extern int early_write_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 val);
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extern int early_write_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 val);
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extern int early_find_capability(struct pci_controller *hose, int bus,
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int dev_fn, int cap);
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@ -104,15 +105,7 @@ extern void setup_grackle(struct pci_controller *hose);
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extern void __init update_bridge_resource(struct pci_dev *dev,
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struct resource *res);
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#else
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#else /* CONFIG_PPC64 */
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/*
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* Structure of a PCI controller (host bridge)
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@ -159,8 +152,8 @@ struct pci_controller {
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* PCI stuff, for nodes representing PCI devices, pointed to
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* by device_node->data.
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*/
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struct pci_controller;
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struct iommu_table;
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struct device_node;
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struct pci_dn {
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int busno; /* pci bus number */
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@ -179,9 +172,9 @@ struct pci_dn {
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int eeh_mode; /* See eeh.h for possible EEH_MODEs */
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int eeh_config_addr;
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int eeh_pe_config_addr; /* new-style partition endpoint address */
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int eeh_check_count; /* # times driver ignored error */
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int eeh_freeze_count; /* # times this device froze up. */
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int eeh_false_positives; /* # times this device reported #ff's */
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int eeh_check_count; /* # times driver ignored error */
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int eeh_freeze_count; /* # times this device froze up. */
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int eeh_false_positives; /* # times this device reported #ff's */
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u32 config_space[16]; /* saved PCI config space */
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#endif
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};
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@ -189,7 +182,7 @@ struct pci_dn {
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/* Get the pointer to a device_node's pci_dn */
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#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
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struct device_node *fetch_dev_dn(struct pci_dev *dev);
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extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
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/* Get a device_node from a pci_dev. This code must be fast except
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* in the case where the sysdata is incorrect and needs to be fixed
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@ -227,14 +220,14 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
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}
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/** Find the bus corresponding to the indicated device node */
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struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
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extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
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/** Remove all of the PCI devices under this bus */
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void pcibios_remove_pci_devices(struct pci_bus *bus);
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extern void pcibios_remove_pci_devices(struct pci_bus *bus);
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/** Discover new pci devices under this bus, and add them */
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void pcibios_add_pci_devices(struct pci_bus * bus);
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void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
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extern void pcibios_add_pci_devices(struct pci_bus *bus);
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extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
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extern int pcibios_remove_root_bus(struct pci_controller *phb);
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@ -270,20 +263,18 @@ extern int pcibios_map_io_space(struct pci_bus *bus);
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#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
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#endif
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#endif /* CONFIG_PPC64 */
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#endif /* CONFIG_PPC64 */
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller*
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pci_find_hose_for_OF_device(struct device_node* node);
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extern struct pci_controller *pci_find_hose_for_OF_device(
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struct device_node* node);
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/* Fill up host controller resources from the OF node */
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extern void
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pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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/* Allocate & free a PCI host bridge structure */
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extern struct pci_controller *
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pcibios_alloc_controller(struct device_node *dev);
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extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
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extern void pcibios_free_controller(struct pci_controller *phb);
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#ifdef CONFIG_PCI
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@ -298,9 +289,7 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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return 0;
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}
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#endif
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#endif /* CONFIG_PCI */
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#endif /* __KERNEL__ */
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
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