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davinci_mdio: Correct bitmask for clock divider value

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The CLKDIV bitfield in the MDIO Control Register is a 16 bit field,
therefore the CLKDIV value may range from 0 to 0xffff.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christian Riesch 2012-02-22 22:07:58 +00:00 committed by David S. Miller
parent b4ad042813
commit 7c3a95a15a
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/ti/davinci_mdio.c
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@ -53,7 +53,7 @@ struct davinci_mdio_regs {
u32 control;
#define CONTROL_IDLE BIT(31)
#define CONTROL_ENABLE BIT(30)
#define CONTROL_MAX_DIV (0xff)
#define CONTROL_MAX_DIV (0xffff)
u32 alive;
u32 link;