clk: tegra: Add fields for override bits
PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -136,6 +136,9 @@ struct pdiv_map {
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* @divm_width: width of the input divider bit field
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* @divp_shift: shift to the post divider bit field
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* @divp_width: width of the post divider bit field
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* @override_divn_shift: shift to the feedback divider bitfield in override reg
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* @override_divm_shift: shift to the input divider bitfield in override reg
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* @override_divp_shift: shift to the post divider bitfield in override reg
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*/
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struct div_nmp {
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u8 divn_shift;
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@ -144,6 +147,9 @@ struct div_nmp {
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u8 divm_width;
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u8 divp_shift;
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u8 divp_width;
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u8 override_divn_shift;
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u8 override_divm_shift;
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u8 override_divp_shift;
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};
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/**
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@ -180,6 +186,8 @@ struct tegra_clk_pll_params {
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u32 aux_reg;
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u32 dyn_ramp_reg;
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u32 ext_misc_reg[3];
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u32 pmc_divnm_reg;
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u32 pmc_divp_reg;
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int stepa_shift;
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int stepb_shift;
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int lock_delay;
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