MIPS: PCI: Multi-node PCI support for Netlogic XLP
On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
John Crispin
parent
cba3b64303
commit
7b53eb4d40
1 changed files with 66 additions and 43 deletions
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@ -46,6 +46,7 @@
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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@ -161,32 +162,38 @@ struct pci_controller nlm_pci_controller = {
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.io_offset = 0x00000000UL,
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};
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static int get_irq_vector(const struct pci_dev *dev)
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static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
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{
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/*
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* For XLP PCIe, there is an IRQ per Link, find out which
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* link the device is on to assign interrupts
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*/
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if (dev->bus->self == NULL)
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return 0;
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struct pci_bus *bus, *p;
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switch (dev->bus->self->devfn) {
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case 0x8:
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return PIC_PCIE_LINK_0_IRQ;
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case 0x9:
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return PIC_PCIE_LINK_1_IRQ;
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case 0xa:
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return PIC_PCIE_LINK_2_IRQ;
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case 0xb:
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return PIC_PCIE_LINK_3_IRQ;
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}
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WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
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return 0;
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/* Find the bridge on bus 0 */
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bus = dev->bus;
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for (p = bus->parent; p && p->number != 0; p = p->parent)
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bus = p;
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return p ? bus->self : NULL;
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}
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static inline int nlm_pci_link_to_irq(int link)
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{
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return PIC_PCIE_LINK_0_IRQ + link;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return get_irq_vector(dev);
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struct pci_dev *lnkdev;
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int lnkslot, lnkfunc;
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/*
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* For XLP PCIe, there is an IRQ per Link, find out which
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* link the device is on to assign interrupts
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*/
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lnkdev = xlp_get_pcie_link(dev);
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if (lnkdev == NULL)
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return 0;
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lnkfunc = PCI_FUNC(lnkdev->devfn);
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lnkslot = PCI_SLOT(lnkdev->devfn);
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return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc));
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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@ -201,45 +208,42 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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* readl/writel.
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*/
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#ifdef __BIG_ENDIAN
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static void xlp_config_pci_bswap(void)
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static void xlp_config_pci_bswap(int node, int link)
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{
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uint64_t pciebase, sysbase;
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int node, i;
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uint64_t nbubase, lnkbase;
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u32 reg;
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/* Chip-0 so node set to 0 */
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node = 0;
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sysbase = nlm_get_bridge_regbase(node);
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nbubase = nlm_get_bridge_regbase(node);
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lnkbase = nlm_get_pcie_base(node, link);
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/*
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* Enable byte swap in hardware. Program each link's PCIe SWAP regions
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* from the link's address ranges.
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*/
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for (i = 0; i < 4; i++) {
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pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
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if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
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continue;
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
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reg | 0xfff);
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
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}
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
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}
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#else
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/* Swap configuration not needed in little-endian mode */
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static inline void xlp_config_pci_bswap(void) {}
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static inline void xlp_config_pci_bswap(int node, int link) {}
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#endif /* __BIG_ENDIAN */
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static int __init pcibios_init(void)
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{
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struct nlm_soc_info *nodep;
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uint64_t pciebase;
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int link, n;
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u32 reg;
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/* Firmware assigns PCI resources */
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pci_set_flags(PCI_PROBE_ONLY);
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pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
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@ -248,7 +252,26 @@ static int __init pcibios_init(void)
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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xlp_config_pci_bswap();
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for (n = 0; n < NLM_NR_NODES; n++) {
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nodep = nlm_get_node(n);
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if (!nodep->coremask)
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continue; /* node does not exist */
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for (link = 0; link < 4; link++) {
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pciebase = nlm_get_pcie_base(n, link);
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if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
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continue;
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xlp_config_pci_bswap(n, link);
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/* put in intpin and irq - u-boot does not */
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reg = nlm_read_pci_reg(pciebase, 0xf);
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reg &= ~0x1fu;
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reg |= (1 << 8) | nlm_pci_link_to_irq(link);
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nlm_write_pci_reg(pciebase, 0xf, reg);
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pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
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}
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}
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set_io_port_base(CKSEG1);
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nlm_pci_controller.io_map_base = CKSEG1;
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