Clock framework and driver fixes, all of which fix user-visible
regressions. There is a single framework fix that prevents dereferencing
a NULL pointer when calling clk_get. The range of fixes for clock driver
regressions spans memory leak fixes, touching the wrong registers that
cause things to explode, misconfigured clock rates that result in
non-responsive devices and even some boot failures. The most benign fix
is DT binding doc typo. It is a stable ABI exposed from the kernel that
was introduced in -rc1, so best to fix it now.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTEpHGAAoJEDqPOy9afJhJBHUP/3rkQWvFA216EO8zhIQMnJS/
Xw6S+jufccG2u4arJsVUTJ2n3Xak0J/LNU2MYRHrIc+xLgk5KdntmcmQ2qcEeh46
YOp9UYx1qACy4FtFG6yjZibmD6sZ9YWJrEn58xeBUXZck3aoV8MDblMmY5xZu0wM
EOI8HD/RNmLe8SwXfJglmlsUuv5n5IOSw73Dqkjj5J4/mGUh2BqvItDJPfnt23fI
EgURLYRTnQ8xBYfvV0F+8HOFUqYegRuJO9P9/ykfdzSaJZD+96jnImaaeOr34z7d
xL/HXQEkK/kft5iF70Hnhcb24j/JVdrC22+TZi16YwIODLeCyaIHBO/UsZ/0f5rY
MHz1Y4m8ZWnH3RCvfFJ2VJqAzb5UmKbRGS6Sg8SBdx4icBSvvWudIHeql4StTGZ3
Hgi2WkJeLO+PCwbpECNtDdhtPZV6H3r+AFyllcEx+V8AK0U25vOhOg+2ijJSPrW7
1gLQX+Yyco+zjcV2umGw/l3pfm/JjpE2IfJxtgMS2C84+/kGGgppPHiZPQzowpKT
ClPTziZjkzFP4ZE1fCEWGidCyqyjKr69TasIA0gxhI6h4aVvr5sRGhfgtEfMrbE9
dLFoMeQ7EMmZdMRX0O9IJuXt79yPs4Z5v9oX32C18Qyz7I04E6UBuueRgMJCglZP
3NoIkEbGeHQdD6YpihEQ
=zck4
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework fixes from Mike Turquette:
"Clock framework and driver fixes, all of which fix user-visible
regressions.
There is a single framework fix that prevents dereferencing a NULL
pointer when calling clk_get. The range of fixes for clock driver
regressions spans memory leak fixes, touching the wrong registers that
cause things to explode, misconfigured clock rates that result in
non-responsive devices and even some boot failures. The most benign
fix is DT binding doc typo. It is a stable ABI exposed from the
kernel that was introduced in -rc1, so best to fix it now"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
clk:at91: Fix memory leak in of_at91_clk_master_setup()
clk: nomadik: fix multiplatform problem
clk: Correct handling of NULL clk in __clk_{get, put}
clk: shmobile: Fix typo in MSTP clock DT bindings
clk: shmobile: rcar-gen2: Fix qspi divisor
clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocks
clk: tegra124: remove gr2d and gr3d clocks
clk: tegra: Fix vic03 mux index
clk: shmobile: rcar-gen2: Fix qspi divisor
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: tegra: use max divider if divider overflows
clk: tegra: cclk_lp has a pllx/2 divider
clk: tegra: fix sdmmc clks on Tegra1x4
clk: tegra: fix host1x clock on Tegra124
clk: tegra: PLLD2 fixes for hdmi
clk: tegra: Fix PLLD mnp table
clk: tegra: Fix PLLP rate table
clk: tegra: Correct clock number for UARTE
clk: tegra: Add missing Tegra20 fuse clks
ARM: keystone: dts: fix clkvcp3 control register address
...
This commit is contained in:
Linus Torvalds
commit
7abd42eab3
19 changed files with 116 additions and 95 deletions
|
|
@ -21,9 +21,9 @@ Required Properties:
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|||
must appear in the same order as the output clocks.
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- #clock-cells: Must be 1
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- clock-output-names: The name of the clocks as free-form strings
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- renesas,indices: Indices of the gate clocks into the group (0 to 31)
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- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
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The clocks, clock-output-names and renesas,indices properties contain one
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The clocks, clock-output-names and renesas,clock-indices properties contain one
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entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
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gate clocks must not be declared.
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|
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@ -612,7 +612,7 @@ clocks {
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-3";
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reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
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reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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@ -242,7 +242,7 @@ of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
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irq = irq_of_parse_and_map(np, 0);
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if (!irq)
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return;
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goto out_free_characteristics;
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clk = at91_clk_register_master(pmc, irq, name, num_parents,
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parent_names, layout,
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@ -494,6 +494,9 @@ static const struct file_operations nomadik_src_clk_debugfs_ops = {
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static int __init nomadik_src_clk_init_debugfs(void)
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{
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/* Vital for multiplatform */
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if (!src_base)
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return -ENODEV;
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src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
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src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
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debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
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@ -2226,24 +2226,25 @@ EXPORT_SYMBOL_GPL(devm_clk_unregister);
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*/
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int __clk_get(struct clk *clk)
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{
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if (clk && !try_module_get(clk->owner))
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return 0;
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if (clk) {
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if (!try_module_get(clk->owner))
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return 0;
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kref_get(&clk->ref);
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kref_get(&clk->ref);
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}
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return 1;
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}
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void __clk_put(struct clk *clk)
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{
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if (WARN_ON_ONCE(IS_ERR(clk)))
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if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
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return;
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clk_prepare_lock();
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kref_put(&clk->ref, __clk_release);
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clk_prepare_unlock();
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if (clk)
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module_put(clk->owner);
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module_put(clk->owner);
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}
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/*** clk rate change notifiers ***/
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@ -179,6 +179,7 @@ static struct clk *clk_register_psc(struct device *dev,
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init.name = name;
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init.ops = &clk_psc_ops;
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init.flags = 0;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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@ -141,13 +141,6 @@ static const struct coreclk_soc_desc a370_coreclks = {
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.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
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};
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static void __init a370_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &a370_coreclks);
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}
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CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
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a370_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -168,9 +161,15 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
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{ }
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};
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static void __init a370_clk_gating_init(struct device_node *np)
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static void __init a370_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, a370_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,armada-370-gating-clock");
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mvebu_coreclk_setup(np, &a370_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, a370_gating_desc);
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}
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CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
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a370_clk_gating_init);
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CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init);
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@ -158,13 +158,6 @@ static const struct coreclk_soc_desc axp_coreclks = {
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.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
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};
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static void __init axp_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &axp_coreclks);
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}
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CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
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axp_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -202,9 +195,14 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
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{ }
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};
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static void __init axp_clk_gating_init(struct device_node *np)
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static void __init axp_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, axp_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
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mvebu_coreclk_setup(np, &axp_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, axp_gating_desc);
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}
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CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
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axp_clk_gating_init);
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CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
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@ -154,12 +154,6 @@ static const struct coreclk_soc_desc dove_coreclks = {
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.num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
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};
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static void __init dove_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &dove_coreclks);
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}
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CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -186,9 +180,14 @@ static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
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{ }
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};
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static void __init dove_clk_gating_init(struct device_node *np)
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static void __init dove_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, dove_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
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mvebu_coreclk_setup(np, &dove_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, dove_gating_desc);
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}
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CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
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dove_clk_gating_init);
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CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
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@ -193,13 +193,6 @@ static const struct coreclk_soc_desc kirkwood_coreclks = {
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init kirkwood_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &kirkwood_coreclks);
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}
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CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
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kirkwood_coreclk_init);
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static const struct coreclk_soc_desc mv88f6180_coreclks = {
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.get_tclk_freq = kirkwood_get_tclk_freq,
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.get_cpu_freq = mv88f6180_get_cpu_freq,
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|
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@ -208,13 +201,6 @@ static const struct coreclk_soc_desc mv88f6180_coreclks = {
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init mv88f6180_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &mv88f6180_coreclks);
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}
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CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
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mv88f6180_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -239,9 +225,21 @@ static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
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{ }
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};
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static void __init kirkwood_clk_gating_init(struct device_node *np)
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static void __init kirkwood_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, kirkwood_gating_desc);
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struct device_node *cgnp =
|
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of_find_compatible_node(NULL, NULL, "marvell,kirkwood-gating-clock");
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if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock"))
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mvebu_coreclk_setup(np, &mv88f6180_coreclks);
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else
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mvebu_coreclk_setup(np, &kirkwood_coreclks);
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|
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if (cgnp)
|
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mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
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}
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CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
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kirkwood_clk_gating_init);
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CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
|
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kirkwood_clk_init);
|
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CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock",
|
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kirkwood_clk_init);
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|
|
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|||
|
|
@ -186,7 +186,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
|
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const char *name)
|
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{
|
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const struct clk_div_table *table = NULL;
|
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const char *parent_name = "main";
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const char *parent_name;
|
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unsigned int shift;
|
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unsigned int mult = 1;
|
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unsigned int div = 1;
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|
|
@ -201,23 +201,31 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
|
|||
* the multiplier value.
|
||||
*/
|
||||
u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
|
||||
parent_name = "main";
|
||||
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
|
||||
} else if (!strcmp(name, "pll1")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll1_mult / 2;
|
||||
} else if (!strcmp(name, "pll3")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll3_mult;
|
||||
} else if (!strcmp(name, "lb")) {
|
||||
parent_name = "pll1_div2";
|
||||
div = cpg_mode & BIT(18) ? 36 : 24;
|
||||
} else if (!strcmp(name, "qspi")) {
|
||||
parent_name = "pll1_div2";
|
||||
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
|
||||
? 16 : 20;
|
||||
? 8 : 10;
|
||||
} else if (!strcmp(name, "sdh")) {
|
||||
parent_name = "pll1_div2";
|
||||
table = cpg_sdh_div_table;
|
||||
shift = 8;
|
||||
} else if (!strcmp(name, "sd0")) {
|
||||
parent_name = "pll1_div2";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 4;
|
||||
} else if (!strcmp(name, "sd1")) {
|
||||
parent_name = "pll1_div2";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 0;
|
||||
} else if (!strcmp(name, "z")) {
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
|
|||
return 0;
|
||||
|
||||
if (divider_ux1 > get_max_div(divider))
|
||||
return -EINVAL;
|
||||
return get_max_div(divider);
|
||||
|
||||
return divider_ux1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -180,9 +180,13 @@ enum clk_id {
|
|||
tegra_clk_sbc6_8,
|
||||
tegra_clk_sclk,
|
||||
tegra_clk_sdmmc1,
|
||||
tegra_clk_sdmmc1_8,
|
||||
tegra_clk_sdmmc2,
|
||||
tegra_clk_sdmmc2_8,
|
||||
tegra_clk_sdmmc3,
|
||||
tegra_clk_sdmmc3_8,
|
||||
tegra_clk_sdmmc4,
|
||||
tegra_clk_sdmmc4_8,
|
||||
tegra_clk_se,
|
||||
tegra_clk_soc_therm,
|
||||
tegra_clk_sor0,
|
||||
|
|
|
|||
|
|
@ -371,9 +371,7 @@ static const char *mux_pllp3_pllc_clkm[] = {
|
|||
static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
|
||||
"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
|
||||
};
|
||||
static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
|
||||
};
|
||||
#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
|
||||
|
||||
static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
|
||||
"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
|
||||
|
|
@ -465,6 +463,10 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
|
||||
MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
|
||||
MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
|
||||
MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8),
|
||||
MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8),
|
||||
MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8),
|
||||
MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8),
|
||||
MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
|
||||
MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
|
||||
MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
|
||||
|
|
@ -492,7 +494,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
|
||||
UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
|
||||
UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
|
||||
UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),
|
||||
UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
|
||||
XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
|
||||
XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
|
||||
XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
|
|||
ARRAY_SIZE(cclk_lp_parents),
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + CCLKLP_BURST_POLICY,
|
||||
0, 4, 8, 9, NULL);
|
||||
TEGRA_DIVIDER_2, 4, 8, 9, NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -682,12 +682,12 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
|
||||
[tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
|
||||
[tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
|
||||
[tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
|
||||
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
|
||||
[tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
|
||||
[tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
|
||||
[tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
|
||||
[tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
|
||||
[tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
|
||||
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
|
||||
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
|
||||
[tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
|
||||
[tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
|
||||
[tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
|
||||
|
|
@ -723,7 +723,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
|
||||
[tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
|
||||
[tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
|
||||
[tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
|
||||
[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
|
||||
[tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
|
||||
[tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
|
||||
[tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
|
||||
|
|
|
|||
|
|
@ -516,11 +516,11 @@ static struct div_nmp pllp_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{12000000, 216000000, 432, 12, 1, 8},
|
||||
{13000000, 216000000, 432, 13, 1, 8},
|
||||
{16800000, 216000000, 360, 14, 1, 8},
|
||||
{19200000, 216000000, 360, 16, 1, 8},
|
||||
{26000000, 216000000, 432, 26, 1, 8},
|
||||
{12000000, 408000000, 408, 12, 0, 8},
|
||||
{13000000, 408000000, 408, 13, 0, 8},
|
||||
{16800000, 408000000, 340, 14, 0, 8},
|
||||
{19200000, 408000000, 340, 16, 0, 8},
|
||||
{26000000, 408000000, 408, 26, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
|
|
@ -570,6 +570,15 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
};
|
||||
|
||||
static struct div_nmp plld_nmp = {
|
||||
.divm_shift = 0,
|
||||
.divm_width = 5,
|
||||
.divn_shift = 8,
|
||||
.divn_width = 11,
|
||||
.divp_shift = 20,
|
||||
.divp_width = 3,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{12000000, 216000000, 864, 12, 4, 12},
|
||||
{13000000, 216000000, 864, 13, 4, 12},
|
||||
|
|
@ -603,19 +612,18 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.div_nmp = &pllp_nmp,
|
||||
.div_nmp = &plld_nmp,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
|
||||
{ 12000000, 148500000, 99, 1, 8},
|
||||
{ 12000000, 594000000, 99, 1, 1},
|
||||
{ 13000000, 594000000, 91, 1, 1}, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 1}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 1}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 1}, /* actual: 591.5 MHz */
|
||||
{ 12000000, 594000000, 99, 1, 2},
|
||||
{ 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -753,21 +761,19 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
|
||||
[tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
|
||||
[tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
|
||||
[tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
|
||||
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
|
||||
[tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
|
||||
[tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
|
||||
[tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
|
||||
[tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
|
||||
[tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
|
||||
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
|
||||
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
|
||||
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
|
||||
[tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
|
||||
[tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true },
|
||||
[tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
|
||||
[tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
|
||||
[tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true },
|
||||
[tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
|
||||
[tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
|
||||
[tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
|
||||
[tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
|
||||
[tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
|
||||
[tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
|
||||
[tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
|
||||
|
|
@ -794,7 +800,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
|
||||
[tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
|
||||
[tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
|
||||
[tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
|
||||
[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
|
||||
[tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
|
||||
[tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
|
||||
[tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
|
||||
|
|
@ -1286,9 +1292,9 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
|
|||
clk_register_clkdev(clk, "pll_d2", NULL);
|
||||
clks[TEGRA124_CLK_PLL_D2] = clk;
|
||||
|
||||
/* PLLD2_OUT0 ?? */
|
||||
/* PLLD2_OUT0 */
|
||||
clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
CLK_SET_RATE_PARENT, 1, 1);
|
||||
clk_register_clkdev(clk, "pll_d2_out0", NULL);
|
||||
clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
|
||||
|
||||
|
|
|
|||
|
|
@ -574,6 +574,8 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
|
||||
[tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
|
||||
[tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
|
||||
[tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
|
||||
[tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
|
||||
};
|
||||
|
||||
static unsigned long tegra20_clk_measure_input_freq(void)
|
||||
|
|
|
|||
|
|
@ -36,10 +36,10 @@
|
|||
#define TEGRA124_CLK_PWM 17
|
||||
#define TEGRA124_CLK_I2S2 18
|
||||
/* 20 (register bit affects vi and vi_sensor) */
|
||||
#define TEGRA124_CLK_GR_2D 21
|
||||
/* 21 */
|
||||
#define TEGRA124_CLK_USBD 22
|
||||
#define TEGRA124_CLK_ISP 23
|
||||
#define TEGRA124_CLK_GR_3D 24
|
||||
/* 26 */
|
||||
/* 25 */
|
||||
#define TEGRA124_CLK_DISP2 26
|
||||
#define TEGRA124_CLK_DISP1 27
|
||||
|
|
|
|||
Loading…
Reference in a new issue