x86: L3 cache index disable for 2.6.26, cleanups
No change in functionality. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
parent
8cb22bcb1f
commit
7a4983bb5f
1 changed files with 59 additions and 52 deletions
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@ -253,14 +253,16 @@ static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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static void __cpuinit amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
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static void __cpuinit
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amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
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{
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if (index < 3)
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return;
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this_leaf->can_disable = 1;
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}
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static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
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static int
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__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
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{
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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@ -271,19 +273,20 @@ static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_le
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amd_cpuid4(index, &eax, &ebx, &ecx);
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if (boot_cpu_data.x86 >= 0x10)
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amd_check_l3_disable(index, this_leaf);
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} else
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cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
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} else {
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cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
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}
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if (eax.split.type == CACHE_TYPE_NULL)
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return -EIO; /* better error ? */
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this_leaf->eax = eax;
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this_leaf->ebx = ebx;
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this_leaf->ecx = ecx;
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this_leaf->size = (ecx.split.number_of_sets + 1) *
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(ebx.split.coherency_line_size + 1) *
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(ebx.split.physical_line_partition + 1) *
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(ebx.split.ways_of_associativity + 1);
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this_leaf->size = (ecx.split.number_of_sets + 1) *
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(ebx.split.coherency_line_size + 1) *
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(ebx.split.physical_line_partition + 1) *
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(ebx.split.ways_of_associativity + 1);
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return 0;
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}
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@ -649,59 +652,63 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
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}
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}
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
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{
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struct pci_dev *dev;
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if (this_leaf->can_disable) {
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int i;
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ssize_t ret = 0;
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int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
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dev = k8_northbridges[node];
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int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
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struct pci_dev *dev = k8_northbridges[node];
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ssize_t ret = 0;
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int i;
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for (i = 0; i < 2; i++) {
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unsigned int reg;
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pci_read_config_dword(dev, 0x1BC + i * 4, ®);
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ret += sprintf(buf, "%sEntry: %d\n", buf, i);
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ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
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buf,
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reg & 0x80000000 ? "Disabled" : "Allowed",
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reg & 0x40000000 ? "Disabled" : "Allowed");
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ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n", buf,
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(reg & 0x30000) >> 16, reg & 0xfff);
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if (!this_leaf->can_disable)
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return sprintf(buf, "Feature not enabled\n");
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}
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return ret;
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for (i = 0; i < 2; i++) {
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unsigned int reg;
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pci_read_config_dword(dev, 0x1BC + i * 4, ®);
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ret += sprintf(buf, "%sEntry: %d\n", buf, i);
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ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
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buf,
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reg & 0x80000000 ? "Disabled" : "Allowed",
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reg & 0x40000000 ? "Disabled" : "Allowed");
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ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
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buf, (reg & 0x30000) >> 16, reg & 0xfff);
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}
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return sprintf(buf, "Feature not enabled\n");
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return ret;
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}
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static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf, size_t count)
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static ssize_t
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store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
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size_t count)
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{
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struct pci_dev *dev;
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if (this_leaf->can_disable) {
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/* write the MSR value */
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unsigned int ret;
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unsigned int index, val;
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int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
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dev = k8_northbridges[node];
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int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
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struct pci_dev *dev = k8_northbridges[node];
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unsigned int ret, index, val;
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if (strlen(buf) > 15)
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return -EINVAL;
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ret = sscanf(buf, "%x %x", &index, &val);
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if (ret != 2)
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return -EINVAL;
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if (index > 1)
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return -EINVAL;
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val |= 0xc0000000;
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pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
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wbinvd();
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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return 1;
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}
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return 0;
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if (!this_leaf->can_disable)
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return 0;
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/* write the MSR value */
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if (strlen(buf) > 15)
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return -EINVAL;
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ret = sscanf(buf, "%x %x", &index, &val);
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if (ret != 2)
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return -EINVAL;
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if (index > 1)
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return -EINVAL;
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val |= 0xc0000000;
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pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
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wbinvd();
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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return 1;
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}
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struct _cache_attr {
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