Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Moves a test which determines if we actually need to perform a

Browse source 
cacheflush to the right place.  That's a bug which is harmless on UP
but a severe bug on SMP.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2005-02-10 13:54:37 +00:00
parent c6e8b58771
commit 79acf83e50
1 changed files with 7 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
arch/mips/mm/c-r4k.c
View file

@ -376,6 +376,13 @@ static inline void local_r4k_flush_cache_page(void *args)
pmd_t *pmdp;
pte_t *ptep;
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
return;
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pudp = pud_offset(pgdp, page);
@ -432,13 +439,6 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page,
{
struct flush_cache_page_args args;
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
return;
args.vma = vma;
args.page = page;