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ARM: EXYNOS: Add clkdev lookup entry for lcd clock

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The framebuffer driver needs the clock named 'lcd' as its bus
clock but the equivalent clock on Exynos4 is named as 'fimd'.
Hence, create a clkdev lookup entry with the name 'lcd' that
references the 'fimd' clock.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[kgene.kim@samsung.com: rebased on top of latest samsung tree]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tushar Behera 2012-03-12 21:17:02 -07:00 committed by Kukjin Kim
parent efd9960b0e
commit 7902546652
1 changed files with 9 additions and 5 deletions
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14
arch/arm/mach-exynos/clock-exynos4.c
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@ -490,11 +490,6 @@ static struct clk exynos4_init_clocks_off[] = {
.devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
@ -791,6 +786,13 @@ static struct clk exynos4_clk_mdma1 = {
.ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
};
static struct clk exynos4_clk_fimd0 = {
.name = "fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
};
struct clk *exynos4_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
@ -1310,6 +1312,7 @@ static struct clk *exynos4_clk_cdev[] = {
&exynos4_clk_pdma0,
&exynos4_clk_pdma1,
&exynos4_clk_mdma1,
&exynos4_clk_fimd0,
};
static struct clksrc_clk *exynos4_clksrc_cdev[] = {
@ -1336,6 +1339,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),