Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (35 commits) powerpc/5121: make clock debug output more readable powerpc/5xxx: Add common mpc5xxx_get_bus_frequency() function powerpc/5200: Update pcm030.dts to add i2c eeprom and delete cruft powerpc/5200: convert mpc52xx_psc_spi to use cs_control callback fbdev/xilinxfb: Fix improper casting and tighen up probe path usb/ps3: Add missing annotations powerpc: Add memory clobber to mtspr() powerpc: Fix invalid construct in our CPU selection Kconfig ps3rom: Use ps3_system_bus_[gs]et_drvdata() instead of direct access powerpc: Add configurable -Werror for arch/powerpc of_serial: Add UPF_FIXED_TYPE flag drivers/hvc: Add missing __devexit_p() net/ps3: gelic - Add missing annotations powerpc: Introduce macro spin_event_timeout() powerpc/warp: Fix ISA_DMA_THRESHOLD default powerpc/bootwrapper: Custom build options for XPedite52xx targets powerpc/85xx: Add defconfig for X-ES MPC85xx boards powerpc/85xx: Add dts files for X-ES MPC85xx boards powerpc/85xx: Add platform support for X-ES MPC85xx boards 83xx: add support for the kmeter1 board. ...
This commit is contained in:
Linus Torvalds
commit
773d7a09e1
82 changed files with 7907 additions and 216 deletions
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|
@ -2,6 +2,23 @@ menu "Kernel hacking"
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|||
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source "lib/Kconfig.debug"
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config PPC_DISABLE_WERROR
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bool "Don't build arch/powerpc code with -Werror"
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default n
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help
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This option tells the compiler NOT to build the code under
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arch/powerpc with the -Werror flag (which means warnings
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are treated as errors).
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Only enable this if you are hitting a build failure in the
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arch/powerpc code caused by a warning, and you don't feel
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inclined to fix it.
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config PPC_WERROR
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bool
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depends on !PPC_DISABLE_WERROR
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default y
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config PRINT_STACK_DEPTH
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int "Stack depth to print" if DEBUG_KERNEL
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default 64
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|
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|||
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@ -15,6 +15,7 @@
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#include "cuboot.h"
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#define TARGET_85xx
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#define TARGET_HAS_ETH3
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#include "ppcboot.h"
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static bd_t bd;
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@ -27,6 +28,7 @@ static void platform_fixups(void)
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dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
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dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
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dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
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dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr);
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dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
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/* Unfortunately, the specific model number is encoded in the
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|
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@ -167,7 +167,7 @@
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interrupt-parent = <&ipic>;
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interrupts = <39 0x8>;
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phy_type = "ulpi";
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port1;
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port0;
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};
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/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
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usb@23000 {
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@ -152,6 +152,16 @@
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interrupt-parent = <&mpic>;
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dfsrr;
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hwmon@48 {
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compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x00000051>;
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|
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520
arch/powerpc/boot/dts/kmeter1.dts
Normal file
520
arch/powerpc/boot/dts/kmeter1.dts
Normal file
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@ -0,0 +1,520 @@
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/*
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* Keymile KMETER1 Device Tree Source
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*
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* 2008 DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "KMETER1";
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compatible = "keymile,KMETER1";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet_piggy2;
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ethernet1 = &enet_estar1;
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ethernet2 = &enet_estar2;
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ethernet3 = &enet_eth1;
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ethernet4 = &enet_eth2;
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ethernet5 = &enet_eth3;
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ethernet6 = &enet_eth4;
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8360@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; /* Filled in by U-Boot */
|
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bus-frequency = <0>; /* Filled in by U-Boot */
|
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clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
};
|
||||
};
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|
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memory {
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device_type = "memory";
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reg = <0 0>; /* Filled in by U-Boot */
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};
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|
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soc8360@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8360-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x00200000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>; /* Filled in by U-Boot */
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|
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
|
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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serial0: serial@4500 {
|
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cell-index = <0>;
|
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device_type = "serial";
|
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <264000000>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
|
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dma-channel@0 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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ipic: pic@700 {
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "fsl,pq2pro-pic", "fsl,ipic";
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interrupt-controller;
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reg = <0x700 0x100>;
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1400 0x100>;
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compatible = "fsl,mpc8360-par_io";
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num-ports = <7>;
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pio_ucc1: ucc_pin@0 {
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||||
reg = <0>;
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pio-map = <
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||||
/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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0 3 1 0 1 0 /* TxD0 */
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0 4 1 0 1 0 /* TxD1 */
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0 5 1 0 1 0 /* TxD2 */
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0 6 1 0 1 0 /* TxD3 */
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0 9 2 0 1 0 /* RxD0 */
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0 10 2 0 1 0 /* RxD1 */
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0 11 2 0 1 0 /* RxD2 */
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0 12 2 0 1 0 /* RxD3 */
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0 7 1 0 1 0 /* TX_EN */
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0 8 1 0 1 0 /* TX_ER */
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0 15 2 0 1 0 /* RX_DV */
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0 16 2 0 1 0 /* RX_ER */
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0 0 2 0 1 0 /* RX_CLK */
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2 9 1 0 3 0 /* GTX_CLK - CLK10 */
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2 8 2 0 1 0 /* GTX125 - CLK9 */
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||||
>;
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||||
};
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pio_ucc2: ucc_pin@1 {
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reg = <1>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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0 17 1 0 1 0 /* TxD0 */
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0 18 1 0 1 0 /* TxD1 */
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0 19 1 0 1 0 /* TxD2 */
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0 20 1 0 1 0 /* TxD3 */
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0 23 2 0 1 0 /* RxD0 */
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0 24 2 0 1 0 /* RxD1 */
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0 25 2 0 1 0 /* RxD2 */
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0 26 2 0 1 0 /* RxD3 */
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0 21 1 0 1 0 /* TX_EN */
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0 22 1 0 1 0 /* TX_ER */
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0 29 2 0 1 0 /* RX_DV */
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0 30 2 0 1 0 /* RX_ER */
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0 31 2 0 1 0 /* RX_CLK */
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2 2 1 0 2 0 /* GTX_CLK - CLK3 */
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2 3 2 0 1 0 /* GTX125 - CLK4 */
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>;
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};
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pio_ucc4: ucc_pin@3 {
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reg = <3>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
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1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
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1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
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1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
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1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
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1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
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1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
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|
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2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
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|
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pio_ucc5: ucc_pin@4 {
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reg = <4>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
|
||||
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
|
||||
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
|
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3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
|
||||
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
|
||||
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
|
||||
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc6: ucc_pin@5 {
|
||||
reg = <5>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
|
||||
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
|
||||
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
|
||||
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
|
||||
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
|
||||
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
|
||||
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc7: ucc_pin@6 {
|
||||
reg = <6>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
|
||||
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
|
||||
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
|
||||
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
|
||||
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
|
||||
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
|
||||
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc8: ucc_pin@7 {
|
||||
reg = <7>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
|
||||
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
|
||||
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
|
||||
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
|
||||
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
|
||||
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
|
||||
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
|
||||
|
||||
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qe@100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0x100000 0x100000>;
|
||||
reg = <0x100000 0x480>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
brg-frequency = <0>; /* Filled in by U-Boot */
|
||||
bus-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x0000c000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0xc000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
enet_estar1: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
phy-handle = <&phy_estar1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc1>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
enet_estar2: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk4";
|
||||
phy-handle = <&phy_estar2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc2>;
|
||||
};
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
enet_piggy2: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
phy-handle = <&phy_piggy2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc4>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
enet_eth1: ucc@2400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth1>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc5>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
enet_eth2: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc6>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
enet_eth3: ucc@2600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <7>;
|
||||
reg = <0x2600 0x200>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth3>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc7>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
enet_eth4: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth4>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc8>;
|
||||
};
|
||||
|
||||
mdio@3320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3320 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
phy_piggy2: ethernet-phy@00 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
phy_eth1: ethernet-phy@08 {
|
||||
reg = <0x08>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
phy_eth2: ethernet-phy@09 {
|
||||
reg = <0x09>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
phy_eth3: ethernet-phy@0a {
|
||||
reg = <0x0a>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
phy_eth4: ethernet-phy@0b {
|
||||
reg = <0x0b>;
|
||||
};
|
||||
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
phy_estar1: ethernet-phy@10 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
phy_estar2: ethernet-phy@11 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <32 8 33 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
|
||||
|
||||
flash@f0000000,0 {
|
||||
compatible = "cfi-flash";
|
||||
/*
|
||||
* The Intel P30 chip has 2 non-identical chips on
|
||||
* one die, so we need to define 2 seperate regions
|
||||
* that are scanned by physmap_of independantly.
|
||||
*/
|
||||
reg = <0 0x00000000 0x02000000
|
||||
0 0x02000000 0x02000000>; /* Filled in by U-Boot */
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0 0x40000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "env";
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "dtb";
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
partition@a0000 {
|
||||
label = "kernel";
|
||||
reg = <0xa0000 0x300000>;
|
||||
};
|
||||
partition@3a0000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x3a0000 0x800000>;
|
||||
};
|
||||
partition@ba0000 {
|
||||
label = "user";
|
||||
reg = <0xba0000 0x3460000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -17,6 +17,13 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
serial0 = &scc1;
|
||||
serial1 = &scc4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -46,13 +53,13 @@
|
|||
#size-cells = <1>;
|
||||
reg = <0xf0010100 0x40>;
|
||||
|
||||
ranges = <0x0 0x0 0xfe000000 0x2000000
|
||||
ranges = <0x0 0x0 0xff800000 0x00800000
|
||||
0x1 0x0 0xf4500000 0x8000
|
||||
0x3 0x0 0xf8200000 0x8000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "jedec-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
reg = <0x0 0x0 0x00800000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
|
@ -144,7 +151,7 @@
|
|||
reg = <0x119f0 0x10 0x115f0 0x10>;
|
||||
};
|
||||
|
||||
serial@11a00 {
|
||||
scc1: serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
|
|
@ -155,7 +162,7 @@
|
|||
fsl,cpm-command = <0x800000>;
|
||||
};
|
||||
|
||||
serial@11a60 {
|
||||
scc4: serial@11a60 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
|
|
@ -192,7 +199,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@11300 {
|
||||
eth0: ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8272-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
|
|
@ -205,7 +212,7 @@
|
|||
fsl,cpm-command = <0x12000300>;
|
||||
};
|
||||
|
||||
ethernet@11320 {
|
||||
eth1: ethernet@11320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8272-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
|
|
|
|||
|
|
@ -322,6 +322,21 @@
|
|||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
ipic-msi@7c0 {
|
||||
compatible = "fsl,ipic-msi";
|
||||
reg = <0x7c0 0x40>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <0x43 0x8
|
||||
0x4 0x8
|
||||
0x51 0x8
|
||||
0x52 0x8
|
||||
0x56 0x8
|
||||
0x57 0x8
|
||||
0x58 0x8
|
||||
0x59 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
|
|
|
|||
|
|
@ -156,7 +156,7 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@
|
|||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet5 = &enet5;
|
||||
ethernet7 = &enet7;
|
||||
pci1 = &pci1;
|
||||
rapidio0 = &rio0;
|
||||
};
|
||||
|
|
@ -70,8 +72,30 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
partition@0 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00000000 0x01c00000>;
|
||||
};
|
||||
partition@1c00000 {
|
||||
label = "kernel";
|
||||
reg = <0x01c00000 0x002e0000>;
|
||||
};
|
||||
partiton@1ee0000 {
|
||||
label = "dtb";
|
||||
reg = <0x01ee0000 0x00020000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
label = "firmware";
|
||||
reg = <0x01f00000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1f80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01f80000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
|
|
@ -466,6 +490,37 @@
|
|||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy5: ethernet-phy@04 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x04>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy7: ethernet-phy@06 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x6>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
mdio@3520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3520 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
tbi0: tbi-phy@15 {
|
||||
reg = <0x15>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
mdio@3720 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3720 0x38>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
tbi1: tbi-phy@17 {
|
||||
reg = <0x17>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ucc@2200 {
|
||||
|
|
@ -513,6 +568,36 @@
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet5: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&qe_phy5>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet7: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&qe_phy7>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -258,34 +258,16 @@
|
|||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
/* FIXME: EEPROM */
|
||||
eeprom@52 {
|
||||
compatible = "catalyst,24c32";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
|
||||
/* This is only an example device to show the usage of gpios. It maps all available
|
||||
* gpios to the "gpio-provider" device.
|
||||
*/
|
||||
gpio {
|
||||
compatible = "gpio-provider";
|
||||
|
||||
/* mpc52xx exp.con patchfield */
|
||||
gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
|
||||
&gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
|
||||
&gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
|
||||
&gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpt2 0 0 /* timer2 12d x4-4 */
|
||||
&gpt3 0 0 /* timer3 13d x6-4 */
|
||||
&gpt4 0 0 /* timer4 61c x2-16 */
|
||||
&gpt5 0 0 /* timer5 44c x7-11 */
|
||||
&gpt6 0 0 /* timer6 60c x8-15 */
|
||||
&gpt7 0 0 /* timer7 36a x17-9 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
|
|
|
|||
696
arch/powerpc/boot/dts/xcalibur1501.dts
Normal file
696
arch/powerpc/boot/dts/xcalibur1501.dts
Normal file
|
|
@ -0,0 +1,696 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xcalibur1501";
|
||||
compatible = "xes,xcalibur1501", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
|
||||
4 0 0 0xe9000000 0x100000>; /* CS4: USB */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@4,0 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <4 0 0x100000>;
|
||||
bus-width = <32>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@6a {
|
||||
compatible = "plx,pex8648";
|
||||
reg = <0x6a>;
|
||||
};
|
||||
|
||||
/* On-board signals for VID, flash, serial */
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* PMC0/XMC0 signals */
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* PMC1/XMC1 signals */
|
||||
gpio3: gpio@1d {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1d>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* CompactPCI signals (sysen, GA[4:0]) */
|
||||
gpio4: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* CompactPCI J5 GPIO and FAL/DEG/PRST */
|
||||
gpio5: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 front panel 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 front panel 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 3 PICMG2.16 backplane port 0 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 4 PICMG2.16 backplane port 1 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*
|
||||
* PCI Express controller 2 @ ef009000 is not used.
|
||||
* This would have been pci1 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8648 PCIe switch */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
466
arch/powerpc/boot/dts/xpedite5200.dts
Normal file
466
arch/powerpc/boot/dts/xpedite5200.dts
Normal file
|
|
@ -0,0 +1,466 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
|
||||
* Based on TQM8548 device tree
|
||||
*
|
||||
* XPedite5200 PrPMC/XMC module based on MPC8548E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "xes,xpedite5200";
|
||||
compatible = "xes,xpedite5200", "xes,MPC8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
soc@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
/* On-card I2C */
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
/*
|
||||
* Board GPIO:
|
||||
* 0: BRD_CFG0 (1: P14 IO present)
|
||||
* 1: BRD_CFG1 (1: FP ethernet present)
|
||||
* 2: BRD_CFG2 (1: XMC IO present)
|
||||
* 3: XMC root complex indicator
|
||||
* 4: Flash boot device indicator
|
||||
* 5: Flash write protect enable
|
||||
* 6: PMC monarch indicator
|
||||
* 7: PMC EREADY
|
||||
*/
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* P14 GPIO */
|
||||
gpio2: gpio@19 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x19>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,at24c16";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
dtt@48 {
|
||||
compatible = "maxim,max1237";
|
||||
reg = <0x34>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Off-card I2C */
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC1: Front panel port 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC2: Front panel port 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC3: Rear panel port 2 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC4: Rear panel port 3 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR boot flash
|
||||
1 0x0 0xf8000000 0x04000000 // NOR expansion flash
|
||||
2 0x0 0xef800000 0x00010000 // NAND CE1
|
||||
3 0x0 0xef840000 0x00010000 // NAND CE2
|
||||
>;
|
||||
|
||||
nor-boot@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Primary OS";
|
||||
reg = <0x00000000 0x180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "Secondary OS";
|
||||
reg = <0x00180000 0x180000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "User";
|
||||
reg = <0x00300000 0x3c80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Filesystem";
|
||||
reg = <0x00000000 0x3f80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Alternate boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xes,address-ctl-nand";
|
||||
reg = <2 0x0 0x10000>;
|
||||
cle-line = <0x8>; /* CLE tied to A3 */
|
||||
ale-line = <0x10>; /* ALE tied to A4 */
|
||||
|
||||
/* U-Boot should fix this up */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC interface */
|
||||
pci0: pci@ef008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xef008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
|
||||
0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
|
||||
};
|
||||
|
||||
/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
|
||||
};
|
||||
506
arch/powerpc/boot/dts/xpedite5200_xmon.dts
Normal file
506
arch/powerpc/boot/dts/xpedite5200_xmon.dts
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
|
||||
* Based on TQM8548 device tree
|
||||
*
|
||||
* XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
|
||||
* xMon boot loader memory map which differs from U-Boot's.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "xes,xpedite5200";
|
||||
compatible = "xes,xpedite5200", "xes,MPC8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
form-factor = "PMC/XMC";
|
||||
boot-bank = <0x0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; // Filled in by boot loader
|
||||
};
|
||||
|
||||
soc@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
/* On-card I2C */
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
/*
|
||||
* Board GPIO:
|
||||
* 0: BRD_CFG0 (1: P14 IO present)
|
||||
* 1: BRD_CFG1 (1: FP ethernet present)
|
||||
* 2: BRD_CFG2 (1: XMC IO present)
|
||||
* 3: XMC root complex indicator
|
||||
* 4: Flash boot device indicator
|
||||
* 5: Flash write protect enable
|
||||
* 6: PMC monarch indicator
|
||||
* 7: PMC EREADY
|
||||
*/
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* P14 GPIO */
|
||||
gpio2: gpio@19 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x19>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,at24c16";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
dtt@48 {
|
||||
compatible = "maxim,max1237";
|
||||
reg = <0x34>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Off-card I2C */
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC1: Front panel port 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC2: Front panel port 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC3: Rear panel port 2 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC4: Rear panel port 3 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <9600>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <9600>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xf8000000 0x08000000 // NOR boot flash
|
||||
1 0x0 0xf0000000 0x08000000 // NOR expansion flash
|
||||
2 0x0 0xe8000000 0x00010000 // NAND CE1
|
||||
3 0x0 0xe8010000 0x00010000 // NAND CE2
|
||||
>;
|
||||
|
||||
nor-boot@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Primary OS";
|
||||
reg = <0x00000000 0x180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "Secondary OS";
|
||||
reg = <0x00180000 0x180000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "User";
|
||||
reg = <0x00300000 0x3c80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Filesystem";
|
||||
reg = <0x00000000 0x3f80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Alternate boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xes,address-ctl-nand";
|
||||
reg = <2 0x0 0x10000>;
|
||||
cle-line = <0x8>; /* CLE tied to A3 */
|
||||
ale-line = <0x10>; /* ALE tied to A4 */
|
||||
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC interface */
|
||||
pci0: pci@ef008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xef008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
/* XMC PCIe */
|
||||
pci1: pcie@ef00a000 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x00000 0 0 1 &mpic 0 1
|
||||
0x00000 0 0 2 &mpic 1 1
|
||||
0x00000 0 0 3 &mpic 2 1
|
||||
0x00000 0 0 4 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
|
||||
clock-frequency = <33333333>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xef00a000 0x1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xc0000000 0x02000000 0
|
||||
0xc0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0x01000000 0
|
||||
0x00000000 0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Needed for dtbImage boot wrapper compatibility */
|
||||
chosen {
|
||||
linux,stdout-path = &serial0;
|
||||
};
|
||||
};
|
||||
640
arch/powerpc/boot/dts/xpedite5301.dts
Normal file
640
arch/powerpc/boot/dts/xpedite5301.dts
Normal file
|
|
@ -0,0 +1,640 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5301 PMC/XMC module based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5301";
|
||||
compatible = "xes,xpedite5301", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
form-factor = "PMC/XMC";
|
||||
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 2, wired to XMC P15 connector */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8112 for PMC interface */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
707
arch/powerpc/boot/dts/xpedite5330.dts
Normal file
707
arch/powerpc/boot/dts/xpedite5330.dts
Normal file
|
|
@ -0,0 +1,707 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5330 3U CompactPCI module based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5330";
|
||||
compatible = "xes,xpedite5330", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
form-factor = "3U CompactPCI";
|
||||
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
pmcslots {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmcslot@0 {
|
||||
cell-index = <0>;
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* monarch;
|
||||
* module-present;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
xmcslots {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
xmcslot@0 {
|
||||
cell-index = <0>;
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* module-present;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
cpci {
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* system-controller;
|
||||
*/
|
||||
system-controller;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
|
||||
pci0: pcie@ef008000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef008000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x01000000 0x0 0x0
|
||||
0x01000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 2, PMC module via PEX8112 bridge */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, XMC P15 */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
638
arch/powerpc/boot/dts/xpedite5370.dts
Normal file
638
arch/powerpc/boot/dts/xpedite5370.dts
Normal file
|
|
@ -0,0 +1,638 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5370 3U VPX single-board computer based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5370";
|
||||
compatible = "xes,xpedite5370", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 2, wired to VPX P1,P2 backplane */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8518 PCIe switch */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -225,6 +225,10 @@ asp834x-redboot)
|
|||
platformo="$object/fixed-head.o $object/redboot-83xx.o"
|
||||
binary=y
|
||||
;;
|
||||
xpedite52*)
|
||||
link_address='0x1400000'
|
||||
platformo=$object/cuboot-85xx.o
|
||||
;;
|
||||
esac
|
||||
|
||||
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
|
||||
|
|
|
|||
908
arch/powerpc/configs/83xx/kmeter1_defconfig
Normal file
908
arch/powerpc/configs/83xx/kmeter1_defconfig
Normal file
|
|
@ -0,0 +1,908 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.28
|
||||
# Fri Apr 3 10:34:33 2009
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
|
||||
#
|
||||
# Processor support
|
||||
#
|
||||
CONFIG_6xx=y
|
||||
# CONFIG_PPC_85xx is not set
|
||||
# CONFIG_PPC_8xx is not set
|
||||
# CONFIG_40x is not set
|
||||
# CONFIG_44x is not set
|
||||
# CONFIG_E200 is not set
|
||||
CONFIG_PPC_FPU=y
|
||||
# CONFIG_FSL_EMB_PERFMON is not set
|
||||
# CONFIG_ALTIVEC is not set
|
||||
CONFIG_PPC_STD_MMU=y
|
||||
CONFIG_PPC_STD_MMU_32=y
|
||||
# CONFIG_PPC_MM_SLICES is not set
|
||||
# CONFIG_SMP is not set
|
||||
CONFIG_PPC32=y
|
||||
CONFIG_WORD_SIZE=32
|
||||
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_MMU=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
|
||||
CONFIG_IRQ_PER_CPU=y
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
|
||||
CONFIG_LOCKDEP_SUPPORT=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_ARCH_HAS_ILOG2_U32=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
|
||||
CONFIG_PPC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_NVRAM=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
|
||||
CONFIG_PPC_OF=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_PPC_UDBG_16550=y
|
||||
# CONFIG_GENERIC_TBSYNC is not set
|
||||
CONFIG_AUDIT_ARCH=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_DEFAULT_UIMAGE=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
# CONFIG_PPC_DCR_NATIVE is not set
|
||||
# CONFIG_PPC_DCR_MMIO is not set
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_LOCK_KERNEL=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_SYSVIPC_SYSCTL=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_CGROUPS is not set
|
||||
# CONFIG_GROUP_SCHED is not set
|
||||
# CONFIG_SYSFS_DEPRECATED_V2 is not set
|
||||
# CONFIG_RELAY is not set
|
||||
# CONFIG_NAMESPACES is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_COMPAT_BRK=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_ANON_INODES=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SIGNALFD=y
|
||||
CONFIG_TIMERFD=y
|
||||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
# CONFIG_MARKERS is not set
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_IOREMAP_PROT=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
|
||||
CONFIG_SLABINFO=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_MODULE_FORCE_LOAD is not set
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_MODULE_FORCE_UNLOAD is not set
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_KMOD=y
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
# CONFIG_IOSCHED_AS is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_DEFAULT_AS is not set
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
CONFIG_DEFAULT_NOOP=y
|
||||
CONFIG_DEFAULT_IOSCHED="noop"
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
# Platform support
|
||||
#
|
||||
CONFIG_PPC_MULTIPLATFORM=y
|
||||
CONFIG_CLASSIC32=y
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_MPC5121_ADS is not set
|
||||
# CONFIG_MPC5121_GENERIC is not set
|
||||
# CONFIG_PPC_MPC52xx is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
# CONFIG_PPC_CELL is not set
|
||||
# CONFIG_PPC_CELL_NATIVE is not set
|
||||
# CONFIG_PPC_82xx is not set
|
||||
# CONFIG_PQ2ADS is not set
|
||||
CONFIG_PPC_83xx=y
|
||||
# CONFIG_MPC831x_RDB is not set
|
||||
# CONFIG_MPC832x_MDS is not set
|
||||
# CONFIG_MPC832x_RDB is not set
|
||||
# CONFIG_MPC834x_MDS is not set
|
||||
# CONFIG_MPC834x_ITX is not set
|
||||
# CONFIG_MPC836x_MDS is not set
|
||||
# CONFIG_MPC836x_RDK is not set
|
||||
# CONFIG_MPC837x_MDS is not set
|
||||
# CONFIG_MPC837x_RDB is not set
|
||||
# CONFIG_SBC834x is not set
|
||||
# CONFIG_ASP834x is not set
|
||||
CONFIG_KMETER1=y
|
||||
# CONFIG_PPC_86xx is not set
|
||||
# CONFIG_EMBEDDED6xx is not set
|
||||
CONFIG_IPIC=y
|
||||
# CONFIG_MPIC is not set
|
||||
# CONFIG_MPIC_WEIRD is not set
|
||||
# CONFIG_PPC_I8259 is not set
|
||||
# CONFIG_PPC_RTAS is not set
|
||||
# CONFIG_MMIO_NVRAM is not set
|
||||
# CONFIG_PPC_MPC106 is not set
|
||||
# CONFIG_PPC_970_NAP is not set
|
||||
# CONFIG_PPC_INDIRECT_IO is not set
|
||||
# CONFIG_GENERIC_IOMAP is not set
|
||||
# CONFIG_CPU_FREQ is not set
|
||||
# CONFIG_TAU is not set
|
||||
CONFIG_QUICC_ENGINE=y
|
||||
# CONFIG_QE_GPIO is not set
|
||||
# CONFIG_FSL_ULI1575 is not set
|
||||
|
||||
#
|
||||
# Kernel options
|
||||
#
|
||||
# CONFIG_HIGHMEM is not set
|
||||
CONFIG_TICK_ONESHOT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_HAVE_AOUT is not set
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
# CONFIG_IOMMU_HELPER is not set
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_HAS_WALK_MEMORY=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
|
||||
# CONFIG_KEXEC is not set
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
# CONFIG_DISCONTIGMEM_MANUAL is not set
|
||||
# CONFIG_SPARSEMEM_MANUAL is not set
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_MIGRATION=y
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=1
|
||||
CONFIG_BOUNCE=y
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=11
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
CONFIG_EXTRA_TARGETS=""
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_ISA_DMA_API=y
|
||||
|
||||
#
|
||||
# Bus options
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_GENERIC_ISA_DMA=y
|
||||
CONFIG_FSL_SOC=y
|
||||
CONFIG_PPC_PCI_CHOICE=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PCI_DOMAINS is not set
|
||||
# CONFIG_PCI_SYSCALL is not set
|
||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
||||
# CONFIG_HAS_RAPIDIO is not set
|
||||
|
||||
#
|
||||
# Advanced setup
|
||||
#
|
||||
# CONFIG_ADVANCED_OPTIONS is not set
|
||||
|
||||
#
|
||||
# Default settings for advanced configuration options are used
|
||||
#
|
||||
CONFIG_LOWMEM_SIZE=0x30000000
|
||||
CONFIG_PAGE_OFFSET=0xc0000000
|
||||
CONFIG_KERNEL_START=0xc0000000
|
||||
CONFIG_PHYSICAL_START=0x00000000
|
||||
CONFIG_TASK_SIZE=0xc0000000
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_IP_PNP_DHCP is not set
|
||||
# CONFIG_IP_PNP_BOOTP is not set
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
# CONFIG_TCP_MD5SIG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
# CONFIG_IP_DCCP is not set
|
||||
# CONFIG_IP_SCTP is not set
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
CONFIG_STP=m
|
||||
CONFIG_BRIDGE=m
|
||||
# CONFIG_NET_DSA is not set
|
||||
CONFIG_VLAN_8021Q=y
|
||||
# CONFIG_VLAN_8021Q_GVRP is not set
|
||||
# CONFIG_DECNET is not set
|
||||
CONFIG_LLC=m
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_CAN is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
# CONFIG_NET_9P is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
# CONFIG_CONNECTOR is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
CONFIG_MTD_CONCAT=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
CONFIG_MTD_CFI=y
|
||||
# CONFIG_MTD_JEDECPROBE is not set
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
# CONFIG_MTD_CFI_STAA is not set
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
# CONFIG_MTD_PHYSMAP is not set
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
CONFIG_MTD_PHRAM=y
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
|
||||
#
|
||||
# UBI debugging options
|
||||
#
|
||||
CONFIG_MTD_UBI_DEBUG=y
|
||||
# CONFIG_MTD_UBI_DEBUG_MSG is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_PARANOID is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set
|
||||
|
||||
#
|
||||
# Additional UBI debugging messages
|
||||
#
|
||||
# CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_MSG_WL is not set
|
||||
# CONFIG_MTD_UBI_DEBUG_MSG_IO is not set
|
||||
CONFIG_OF_DEVICE=y
|
||||
CONFIG_OF_I2C=y
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_FD is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
# CONFIG_MACINTOSH_DRIVERS is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
CONFIG_TUN=y
|
||||
# CONFIG_VETH is not set
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
CONFIG_MARVELL_PHY=y
|
||||
# CONFIG_DAVICOM_PHY is not set
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_VITESSE_PHY is not set
|
||||
# CONFIG_SMSC_PHY is not set
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_ICPLUS_PHY is not set
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_MDIO_BITBANG is not set
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_IBM_NEW_EMAC_ZMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
# CONFIG_B44 is not set
|
||||
CONFIG_NETDEV_1000=y
|
||||
# CONFIG_GIANFAR is not set
|
||||
CONFIG_UCC_GETH=y
|
||||
# CONFIG_UGETH_MAGIC_PACKET is not set
|
||||
# CONFIG_UGETH_FILTERING is not set
|
||||
# CONFIG_UGETH_TX_ON_DEMAND is not set
|
||||
# CONFIG_MV643XX_ETH is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
|
||||
#
|
||||
# Wireless LAN
|
||||
#
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
# CONFIG_IWLWIFI_LEDS is not set
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=y
|
||||
# CONFIG_HDLC_RAW is not set
|
||||
# CONFIG_HDLC_RAW_ETH is not set
|
||||
# CONFIG_HDLC_CISCO is not set
|
||||
# CONFIG_HDLC_FR is not set
|
||||
# CONFIG_HDLC_PPP is not set
|
||||
|
||||
#
|
||||
# X.25/LAPB support is disabled
|
||||
#
|
||||
CONFIG_HDLC_KM=y
|
||||
CONFIG_FS_UCC_HDLC=y
|
||||
# CONFIG_DLCI is not set
|
||||
CONFIG_PPP=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
# CONFIG_PPP_FILTER is not set
|
||||
# CONFIG_PPP_ASYNC is not set
|
||||
# CONFIG_PPP_SYNC_TTY is not set
|
||||
# CONFIG_PPP_DEFLATE is not set
|
||||
# CONFIG_PPP_BSDCOMP is not set
|
||||
# CONFIG_PPP_MPPE is not set
|
||||
CONFIG_PPPOE=y
|
||||
# CONFIG_PPPOL2TP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
CONFIG_SLHC=y
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
# CONFIG_ISDN is not set
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
# CONFIG_INPUT is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
# CONFIG_SERIAL_UARTLITE is not set
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_OF_PLATFORM is not set
|
||||
# CONFIG_SERIAL_QE is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_NVRAM is not set
|
||||
# CONFIG_GEN_RTC is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
CONFIG_BOOTCOUNT=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
|
||||
#
|
||||
# I2C Hardware Bus support
|
||||
#
|
||||
|
||||
#
|
||||
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||
#
|
||||
CONFIG_I2C_MPC=y
|
||||
# CONFIG_I2C_OCORES is not set
|
||||
# CONFIG_I2C_SIMTEC is not set
|
||||
|
||||
#
|
||||
# External I2C/SMBus adapter drivers
|
||||
#
|
||||
# CONFIG_I2C_PARPORT_LIGHT is not set
|
||||
# CONFIG_I2C_TAOS_EVM is not set
|
||||
|
||||
#
|
||||
# Other I2C/SMBus bus drivers
|
||||
#
|
||||
# CONFIG_I2C_PCA_PLATFORM is not set
|
||||
# CONFIG_I2C_STUB is not set
|
||||
|
||||
#
|
||||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_AT24 is not set
|
||||
# CONFIG_SENSORS_EEPROM is not set
|
||||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
# CONFIG_SENSORS_PCF8591 is not set
|
||||
# CONFIG_SENSORS_MAX6875 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_MCU_MPC8349EMITX is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
# CONFIG_I2C_DEBUG_BUS is not set
|
||||
# CONFIG_I2C_DEBUG_CHIP is not set
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
|
||||
# CONFIG_GPIOLIB is not set
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
# CONFIG_THERMAL_HWMON is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
#
|
||||
# Sonics Silicon Backplane
|
||||
#
|
||||
# CONFIG_SSB is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_DVB_CORE is not set
|
||||
# CONFIG_VIDEO_MEDIA is not set
|
||||
|
||||
#
|
||||
# Multimedia drivers
|
||||
#
|
||||
# CONFIG_DAB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
# CONFIG_EDAC is not set
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
# CONFIG_DMADEVICES is not set
|
||||
CONFIG_UIO=y
|
||||
# CONFIG_UIO_PDRV is not set
|
||||
# CONFIG_UIO_PDRV_GENIRQ is not set
|
||||
# CONFIG_UIO_SMX is not set
|
||||
# CONFIG_UIO_SERCOS3 is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=0
|
||||
CONFIG_JFFS2_FS_WRITEBUFFER=y
|
||||
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
|
||||
# CONFIG_JFFS2_SUMMARY is not set
|
||||
# CONFIG_JFFS2_FS_XATTR is not set
|
||||
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
# CONFIG_JFFS2_LZO is not set
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
# CONFIG_JFFS2_RUBIN is not set
|
||||
# CONFIG_UBIFS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SUNRPC_REGISTER_V4 is not set
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_ACORN_PARTITION is not set
|
||||
# CONFIG_OSF_PARTITION is not set
|
||||
# CONFIG_AMIGA_PARTITION is not set
|
||||
# CONFIG_ATARI_PARTITION is not set
|
||||
# CONFIG_MAC_PARTITION is not set
|
||||
# CONFIG_MSDOS_PARTITION is not set
|
||||
# CONFIG_LDM_PARTITION is not set
|
||||
# CONFIG_SGI_PARTITION is not set
|
||||
# CONFIG_ULTRIX_PARTITION is not set
|
||||
# CONFIG_SUN_PARTITION is not set
|
||||
# CONFIG_KARMA_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
# CONFIG_SYSV68_PARTITION is not set
|
||||
# CONFIG_NLS is not set
|
||||
# CONFIG_DLM is not set
|
||||
CONFIG_UCC_FAST=y
|
||||
CONFIG_UCC=y
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC7 is not set
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAVE_LMB=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_WARN_DEPRECATED=y
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
# CONFIG_LATENCYTOP is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_IRQSTACKS is not set
|
||||
# CONFIG_VIRQ_DEBUG is not set
|
||||
# CONFIG_BOOTX_TEXT is not set
|
||||
# CONFIG_PPC_EARLY_DEBUG is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
# CONFIG_PPC_CLOCK is not set
|
||||
CONFIG_PPC_LIB_RHEAP=y
|
||||
# CONFIG_VIRTUALIZATION is not set
|
||||
1821
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
Normal file
1821
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,11 @@
|
|||
#define _ASM_POWERPC_DELAY_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/time.h>
|
||||
|
||||
/*
|
||||
* Copyright 1996, Paul Mackerras.
|
||||
* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -30,5 +33,38 @@ extern void udelay(unsigned long usecs);
|
|||
#define mdelay(n) udelay((n) * 1000)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* spin_event_timeout - spin until a condition gets true or a timeout elapses
|
||||
* @condition: a C expression to evalate
|
||||
* @timeout: timeout, in microseconds
|
||||
* @delay: the number of microseconds to delay between each evaluation of
|
||||
* @condition
|
||||
*
|
||||
* The process spins until the condition evaluates to true (non-zero) or the
|
||||
* timeout elapses. The return value of this macro is the value of
|
||||
* @condition when the loop terminates. This allows you to determine the cause
|
||||
* of the loop terminates. If the return value is zero, then you know a
|
||||
* timeout has occurred.
|
||||
*
|
||||
* This primary purpose of this macro is to poll on a hardware register
|
||||
* until a status bit changes. The timeout ensures that the loop still
|
||||
* terminates even if the bit never changes. The delay is for devices that
|
||||
* need a delay in between successive reads.
|
||||
*
|
||||
* gcc will optimize out the if-statement if @delay is a constant.
|
||||
*/
|
||||
#define spin_event_timeout(condition, timeout, delay) \
|
||||
({ \
|
||||
typeof(condition) __ret; \
|
||||
unsigned long __loops = tb_ticks_per_usec * timeout; \
|
||||
unsigned long __start = get_tbl(); \
|
||||
while (!(__ret = (condition)) && (tb_ticks_since(__start) <= __loops)) \
|
||||
if (delay) \
|
||||
udelay(delay); \
|
||||
else \
|
||||
cpu_relax(); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_DELAY_H */
|
||||
|
|
|
|||
|
|
@ -95,8 +95,8 @@ struct fsl_lbc_bank {
|
|||
};
|
||||
|
||||
struct fsl_lbc_regs {
|
||||
struct fsl_lbc_bank bank[8];
|
||||
u8 res0[0x28];
|
||||
struct fsl_lbc_bank bank[12];
|
||||
u8 res0[0x8];
|
||||
__be32 mar; /**< UPM Address Register */
|
||||
u8 res1[0x4];
|
||||
__be32 mamr; /**< UPMA Mode Register */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/mpc5xxx.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#include <linux/suspend.h>
|
||||
|
|
@ -268,7 +269,6 @@ struct mpc52xx_intr {
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* mpc52xx_common.c */
|
||||
extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
|
||||
extern void mpc5200_setup_xlb_arbiter(void);
|
||||
extern void mpc52xx_declare_of_platform_devices(void);
|
||||
extern void mpc52xx_map_common_devices(void);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
|
||||
*
|
||||
* Description:
|
||||
* MPC5121 Prototypes and definitions
|
||||
* MPC5xxx Prototypes and definitions
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by
|
||||
|
|
@ -13,10 +13,10 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_POWERPC_MPC512x_H__
|
||||
#define __ASM_POWERPC_MPC512x_H__
|
||||
#ifndef __ASM_POWERPC_MPC5xxx_H__
|
||||
#define __ASM_POWERPC_MPC5xxx_H__
|
||||
|
||||
extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
|
||||
extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node);
|
||||
|
||||
#endif /* __ASM_POWERPC_MPC512x_H__ */
|
||||
#endif /* __ASM_POWERPC_MPC5xxx_H__ */
|
||||
|
||||
|
|
@ -755,7 +755,8 @@
|
|||
#define mfspr(rn) ({unsigned long rval; \
|
||||
asm volatile("mfspr %0," __stringify(rn) \
|
||||
: "=r" (rval)); rval;})
|
||||
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
|
||||
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\
|
||||
: "memory")
|
||||
|
||||
#ifdef __powerpc64__
|
||||
#ifdef CONFIG_PPC_CELL
|
||||
|
|
|
|||
|
|
@ -389,12 +389,14 @@
|
|||
#define ICCR_CACHE 1 /* Cacheable */
|
||||
|
||||
/* Bit definitions for L1CSR0. */
|
||||
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
|
||||
#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
|
||||
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
|
||||
#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
|
||||
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
|
||||
|
||||
/* Bit definitions for L1CSR1. */
|
||||
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
|
||||
#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
|
||||
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
|
||||
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
|
||||
CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
|
||||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
CFLAGS_prom_init.o += -mno-minimal-toc
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -239,6 +239,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
|
|||
ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
|
||||
ori r11,r11,HID0_LRSTK | HID0_BTIC
|
||||
oris r11,r11,HID0_DPM@h
|
||||
BEGIN_MMU_FTR_SECTION
|
||||
oris r11,r11,HID0_HIGH_BAT@h
|
||||
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
|
||||
BEGIN_FTR_SECTION
|
||||
xori r11,r11,HID0_BTIC
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
|
||||
|
|
|
|||
|
|
@ -17,6 +17,40 @@
|
|||
#include <asm/cputable.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
|
||||
_GLOBAL(__e500_icache_setup)
|
||||
mfspr r0, SPRN_L1CSR1
|
||||
andi. r3, r0, L1CSR1_ICE
|
||||
bnelr /* Already enabled */
|
||||
oris r0, r0, L1CSR1_CPE@h
|
||||
ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
|
||||
mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
|
||||
isync
|
||||
blr
|
||||
|
||||
_GLOBAL(__e500_dcache_setup)
|
||||
mfspr r0, SPRN_L1CSR0
|
||||
andi. r3, r0, L1CSR0_DCE
|
||||
bnelr /* Already enabled */
|
||||
msync
|
||||
isync
|
||||
li r0, 0
|
||||
mtspr SPRN_L1CSR0, r0 /* Disable */
|
||||
msync
|
||||
isync
|
||||
li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
|
||||
mtspr SPRN_L1CSR0, r0 /* Invalidate */
|
||||
isync
|
||||
1: mfspr r0, SPRN_L1CSR0
|
||||
andi. r3, r0, L1CSR0_CLFC
|
||||
bne+ 1b /* Wait for lock bits reset */
|
||||
oris r0, r0, L1CSR0_CPE@h
|
||||
ori r0, r0, L1CSR0_DCE
|
||||
msync
|
||||
isync
|
||||
mtspr SPRN_L1CSR0, r0 /* Enable */
|
||||
isync
|
||||
blr
|
||||
|
||||
_GLOBAL(__setup_cpu_e200)
|
||||
/* enable dedicated debug exception handling resources (Debug APU) */
|
||||
mfspr r3,SPRN_HID0
|
||||
|
|
@ -25,7 +59,16 @@ _GLOBAL(__setup_cpu_e200)
|
|||
b __setup_e200_ivors
|
||||
_GLOBAL(__setup_cpu_e500v1)
|
||||
_GLOBAL(__setup_cpu_e500v2)
|
||||
b __setup_e500_ivors
|
||||
mflr r4
|
||||
bl __e500_icache_setup
|
||||
bl __e500_dcache_setup
|
||||
bl __setup_e500_ivors
|
||||
mtlr r4
|
||||
blr
|
||||
_GLOBAL(__setup_cpu_e500mc)
|
||||
b __setup_e500mc_ivors
|
||||
|
||||
mflr r4
|
||||
bl __e500_icache_setup
|
||||
bl __e500_dcache_setup
|
||||
bl __setup_e500mc_ivors
|
||||
mtlr r4
|
||||
blr
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
# Makefile for Kernel-based Virtual Machine module
|
||||
#
|
||||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm
|
||||
|
||||
common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
# Makefile for ppc-specific library files..
|
||||
#
|
||||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
EXTRA_CFLAGS += -mno-minimal-toc
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
# Makefile for the linux ppc-specific parts of the memory manager.
|
||||
#
|
||||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
EXTRA_CFLAGS += -mno-minimal-toc
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
EXTRA_CFLAGS += -mno-minimal-toc
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -43,7 +43,13 @@ static int __init warp_probe(void)
|
|||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "pika,warp");
|
||||
if (!of_flat_dt_is_compatible(root, "pika,warp"))
|
||||
return 0;
|
||||
|
||||
/* For __dma_alloc_coherent */
|
||||
ISA_DMA_THRESHOLD = ~0L;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
define_machine(warp) {
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include <linux/io.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mpc512x.h>
|
||||
#include <asm/mpc5xxx.h>
|
||||
#include <asm/clk_interface.h>
|
||||
|
||||
#undef CLK_DEBUG
|
||||
|
|
@ -83,13 +83,13 @@ static void dump_clocks(void)
|
|||
mutex_lock(&clocks_mutex);
|
||||
printk(KERN_INFO "CLOCKS:\n");
|
||||
list_for_each_entry(p, &clocks, node) {
|
||||
printk(KERN_INFO " %s %ld", p->name, p->rate);
|
||||
pr_info(" %s=%ld", p->name, p->rate);
|
||||
if (p->parent)
|
||||
printk(KERN_INFO " %s %ld", p->parent->name,
|
||||
pr_cont(" %s=%ld", p->parent->name,
|
||||
p->parent->rate);
|
||||
if (p->flags & CLK_HAS_CTRL)
|
||||
printk(KERN_INFO " reg/bit %d/%d", p->reg, p->bit);
|
||||
printk("\n");
|
||||
pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
|
||||
pr_cont("\n");
|
||||
}
|
||||
mutex_unlock(&clocks_mutex);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
|
||||
#ifndef __MPC512X_H__
|
||||
#define __MPC512X_H__
|
||||
extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
|
||||
extern void __init mpc512x_init_IRQ(void);
|
||||
void __init mpc512x_declare_of_platform_devices(void);
|
||||
#endif /* __MPC512X_H__ */
|
||||
|
|
|
|||
|
|
@ -24,29 +24,6 @@
|
|||
|
||||
#include "mpc512x.h"
|
||||
|
||||
unsigned long
|
||||
mpc512x_find_ips_freq(struct device_node *node)
|
||||
{
|
||||
struct device_node *np;
|
||||
const unsigned int *p_ips_freq = NULL;
|
||||
|
||||
of_node_get(node);
|
||||
while (node) {
|
||||
p_ips_freq = of_get_property(node, "bus-frequency", NULL);
|
||||
if (p_ips_freq)
|
||||
break;
|
||||
|
||||
np = of_get_parent(node);
|
||||
of_node_put(node);
|
||||
node = np;
|
||||
}
|
||||
if (node)
|
||||
of_node_put(node);
|
||||
|
||||
return p_ips_freq ? *p_ips_freq : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(mpc512x_find_ips_freq);
|
||||
|
||||
void __init mpc512x_init_IRQ(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
|
|||
|
|
@ -47,36 +47,6 @@ static DEFINE_SPINLOCK(mpc52xx_lock);
|
|||
static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
|
||||
static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
|
||||
|
||||
/**
|
||||
* mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device
|
||||
* @node: device node
|
||||
*
|
||||
* Returns IPB bus frequency, or 0 if the bus frequency cannot be found.
|
||||
*/
|
||||
unsigned int
|
||||
mpc52xx_find_ipb_freq(struct device_node *node)
|
||||
{
|
||||
struct device_node *np;
|
||||
const unsigned int *p_ipb_freq = NULL;
|
||||
|
||||
of_node_get(node);
|
||||
while (node) {
|
||||
p_ipb_freq = of_get_property(node, "bus-frequency", NULL);
|
||||
if (p_ipb_freq)
|
||||
break;
|
||||
|
||||
np = of_get_parent(node);
|
||||
of_node_put(node);
|
||||
node = np;
|
||||
}
|
||||
if (node)
|
||||
of_node_put(node);
|
||||
|
||||
return p_ipb_freq ? *p_ipb_freq : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(mpc52xx_find_ipb_freq);
|
||||
|
||||
|
||||
/*
|
||||
* Configure the XLB arbiter settings to match what Linux expects.
|
||||
*/
|
||||
|
|
@ -221,7 +191,7 @@ unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
|
|||
if (!mpc52xx_cdm)
|
||||
return 0;
|
||||
|
||||
freq = mpc52xx_find_ipb_freq(node);
|
||||
freq = mpc5xxx_get_bus_frequency(node);
|
||||
if (!freq)
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -96,6 +96,13 @@ config ASP834x
|
|||
This enables support for the Analogue & Micro ASP 83xx
|
||||
board.
|
||||
|
||||
config KMETER1
|
||||
bool "Keymile KMETER1"
|
||||
select DEFAULT_UIMAGE
|
||||
select QUICC_ENGINE
|
||||
help
|
||||
This enables support for the Keymile KMETER1 board.
|
||||
|
||||
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
|
|||
obj-$(CONFIG_SBC834x) += sbc834x.o
|
||||
obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
|
||||
obj-$(CONFIG_ASP834x) += asp834x.o
|
||||
obj-$(CONFIG_KMETER1) += kmeter1.o
|
||||
|
|
|
|||
191
arch/powerpc/platforms/83xx/kmeter1.c
Normal file
191
arch/powerpc/platforms/83xx/kmeter1.c
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* Copyright 2008 DENX Software Engineering GmbH
|
||||
* Author: Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* Description:
|
||||
* Keymile KMETER1 board specific routines.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/ipic.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/qe.h>
|
||||
#include <asm/qe_ic.h>
|
||||
|
||||
#include "mpc83xx.h"
|
||||
|
||||
#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
|
||||
/* ************************************************************************
|
||||
*
|
||||
* Setup the architecture
|
||||
*
|
||||
*/
|
||||
static void __init kmeter1_setup_arch(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("kmeter1_setup_arch()", 0);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
|
||||
mpc83xx_add_bridge(np);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
qe_reset();
|
||||
|
||||
np = of_find_node_by_name(NULL, "par_io");
|
||||
if (np != NULL) {
|
||||
par_io_init(np);
|
||||
of_node_put(np);
|
||||
|
||||
for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
|
||||
par_io_of_config(np);
|
||||
}
|
||||
|
||||
np = of_find_compatible_node(NULL, "network", "ucc_geth");
|
||||
if (np != NULL) {
|
||||
uint svid;
|
||||
|
||||
/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
|
||||
svid = mfspr(SPRN_SVR);
|
||||
if (SVR_REV(svid) == 0x0021) {
|
||||
struct device_node *np_par;
|
||||
struct resource res;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
np_par = of_find_node_by_name(NULL, "par_io");
|
||||
if (np_par == NULL) {
|
||||
printk(KERN_WARNING "%s couldn;t find par_io node\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
/* Map Parallel I/O ports registers */
|
||||
ret = of_address_to_resource(np_par, 0, &res);
|
||||
if (ret) {
|
||||
printk(KERN_WARNING "%s couldn;t map par_io registers\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
base = ioremap(res.start, res.end - res.start + 1);
|
||||
|
||||
/*
|
||||
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
|
||||
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
|
||||
*/
|
||||
setbits32((base + 0xa8), 0x0c003000);
|
||||
|
||||
/*
|
||||
* IMMR + 0x14AC[20:27] = 10101010
|
||||
* (data delay for both UCC's)
|
||||
*/
|
||||
clrsetbits_be32((base + 0xac), 0xff0, 0xaa0);
|
||||
iounmap(base);
|
||||
of_node_put(np_par);
|
||||
}
|
||||
of_node_put(np);
|
||||
}
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
}
|
||||
|
||||
static struct of_device_id kmeter_ids[] = {
|
||||
{ .type = "soc", },
|
||||
{ .compatible = "soc", },
|
||||
{ .compatible = "simple-bus", },
|
||||
{ .type = "qe", },
|
||||
{ .compatible = "fsl,qe", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init kmeter_declare_of_platform_devices(void)
|
||||
{
|
||||
/* Publish the QE devices */
|
||||
of_platform_bus_probe(NULL, kmeter_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices);
|
||||
|
||||
static void __init kmeter1_init_IRQ(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic");
|
||||
if (!np) {
|
||||
np = of_find_node_by_type(NULL, "ipic");
|
||||
if (!np)
|
||||
return;
|
||||
}
|
||||
|
||||
ipic_init(np, 0);
|
||||
|
||||
/* Initialize the default interrupt mapping priorities,
|
||||
* in case the boot rom changed something on us.
|
||||
*/
|
||||
ipic_set_default_priority();
|
||||
of_node_put(np);
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
|
||||
if (!np) {
|
||||
np = of_find_node_by_type(NULL, "qeic");
|
||||
if (!np)
|
||||
return;
|
||||
}
|
||||
qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
|
||||
of_node_put(np);
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
}
|
||||
|
||||
/*
|
||||
* Called very early, MMU is off, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init kmeter1_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "keymile,KMETER1");
|
||||
}
|
||||
|
||||
define_machine(kmeter1) {
|
||||
.name = "KMETER1",
|
||||
.probe = kmeter1_probe,
|
||||
.setup_arch = kmeter1_setup_arch,
|
||||
.init_IRQ = kmeter1_init_IRQ,
|
||||
.get_irq = ipic_get_irq,
|
||||
.restart = mpc83xx_restart,
|
||||
.time_init = mpc83xx_time_init,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
|
@ -22,8 +22,8 @@
|
|||
/* system i/o configuration register low */
|
||||
#define MPC83XX_SICRL_OFFS 0x114
|
||||
#define MPC834X_SICRL_USB_MASK 0x60000000
|
||||
#define MPC834X_SICRL_USB0 0x40000000
|
||||
#define MPC834X_SICRL_USB1 0x20000000
|
||||
#define MPC834X_SICRL_USB0 0x20000000
|
||||
#define MPC834X_SICRL_USB1 0x40000000
|
||||
#define MPC831X_SICRL_USB_MASK 0x00000c00
|
||||
#define MPC831X_SICRL_USB_ULPI 0x00000800
|
||||
#define MPC8315_SICRL_USB_MASK 0x000000fc
|
||||
|
|
|
|||
|
|
@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void)
|
|||
sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
|
||||
|
||||
prop = of_get_property(np, "phy_type", NULL);
|
||||
port1_is_dr = 1;
|
||||
if (prop && (!strcmp(prop, "utmi") ||
|
||||
!strcmp(prop, "utmi_wide"))) {
|
||||
sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
|
||||
sicrh |= MPC834X_SICRH_USB_UTMI;
|
||||
port1_is_dr = 1;
|
||||
port0_is_dr = 1;
|
||||
} else if (prop && !strcmp(prop, "serial")) {
|
||||
dr_mode = of_get_property(np, "dr_mode", NULL);
|
||||
if (dr_mode && !strcmp(dr_mode, "otg")) {
|
||||
sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
|
||||
port1_is_dr = 1;
|
||||
port0_is_dr = 1;
|
||||
} else {
|
||||
sicrl |= MPC834X_SICRL_USB0;
|
||||
sicrl |= MPC834X_SICRL_USB1;
|
||||
}
|
||||
} else if (prop && !strcmp(prop, "ulpi")) {
|
||||
sicrl |= MPC834X_SICRL_USB0;
|
||||
sicrl |= MPC834X_SICRL_USB1;
|
||||
} else {
|
||||
printk(KERN_WARNING "834x USB PHY type not supported\n");
|
||||
}
|
||||
port0_is_dr = 1;
|
||||
of_node_put(np);
|
||||
}
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
|
||||
|
|
|
|||
|
|
@ -35,12 +35,14 @@ config MPC85xx_MDS
|
|||
select DEFAULT_UIMAGE
|
||||
select PHYLIB
|
||||
select HAS_RAPIDIO
|
||||
select SWIOTLB
|
||||
help
|
||||
This option enables support for the MPC85xx MDS board
|
||||
|
||||
config MPC8536_DS
|
||||
bool "Freescale MPC8536 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select SWIOTLB
|
||||
help
|
||||
This option enables support for the MPC8536 DS board
|
||||
|
||||
|
|
@ -49,6 +51,7 @@ config MPC85xx_DS
|
|||
select PPC_I8259
|
||||
select DEFAULT_UIMAGE
|
||||
select FSL_ULI1575
|
||||
select SWIOTLB
|
||||
help
|
||||
This option enables support for the MPC85xx DS (MPC8544 DS) board
|
||||
|
||||
|
|
@ -64,6 +67,16 @@ config KSI8560
|
|||
help
|
||||
This option enables support for the Emerson KSI8560 board
|
||||
|
||||
config XES_MPC85xx
|
||||
bool "X-ES single-board computer"
|
||||
select DEFAULT_UIMAGE
|
||||
help
|
||||
This option enables support for the various single-board
|
||||
computers from Extreme Engineering Solutions (X-ES) based on
|
||||
Freescale MPC85xx processors.
|
||||
Manufacturer: Extreme Engineering Solutions, Inc.
|
||||
URL: <http://www.xes-inc.com/>
|
||||
|
||||
config STX_GP3
|
||||
bool "Silicon Turnkey Express GP3"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -15,3 +15,4 @@ obj-$(CONFIG_SBC8560) += sbc8560.o
|
|||
obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
|
||||
obj-$(CONFIG_KSI8560) += ksi8560.o
|
||||
obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/seq_file.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/lmb.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
|
|
@ -26,6 +27,7 @@
|
|||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/swiotlb.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
|
@ -65,7 +67,9 @@ static void __init mpc8536_ds_setup_arch(void)
|
|||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc8536_ds_setup_arch()", 0);
|
||||
|
|
@ -80,11 +84,22 @@ static void __init mpc8536_ds_setup_arch(void)
|
|||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (lmb_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_pci_dma_ops);
|
||||
}
|
||||
#endif
|
||||
|
||||
printk("MPC8536 DS board from Freescale Semiconductor\n");
|
||||
}
|
||||
|
||||
|
|
@ -102,6 +117,8 @@ static int __init mpc8536_ds_publish_devices(void)
|
|||
}
|
||||
machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices);
|
||||
|
||||
machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/seq_file.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/lmb.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
|
|
@ -30,6 +31,7 @@
|
|||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/swiotlb.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
|
@ -155,7 +157,9 @@ static void __init mpc85xx_ds_setup_arch(void)
|
|||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
|
||||
|
|
@ -171,6 +175,10 @@ static void __init mpc85xx_ds_setup_arch(void)
|
|||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -181,6 +189,13 @@ static void __init mpc85xx_ds_setup_arch(void)
|
|||
mpc85xx_smp_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (lmb_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_pci_dma_ops);
|
||||
}
|
||||
#endif
|
||||
|
||||
printk("MPC85xx DS board from Freescale Semiconductor\n");
|
||||
}
|
||||
|
||||
|
|
@ -217,6 +232,10 @@ machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
|
|||
machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
|
||||
machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
|
||||
|
||||
machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
|
||||
machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
|
||||
machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/lmb.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/atomic.h>
|
||||
|
|
@ -49,6 +50,7 @@
|
|||
#include <asm/qe.h>
|
||||
#include <asm/qe_ic.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/swiotlb.h>
|
||||
|
||||
#undef DEBUG
|
||||
#ifdef DEBUG
|
||||
|
|
@ -155,6 +157,10 @@ static void __init mpc85xx_mds_setup_arch(void)
|
|||
{
|
||||
struct device_node *np;
|
||||
static u8 __iomem *bcsr_regs = NULL;
|
||||
#ifdef CONFIG_PCI
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
|
||||
|
|
@ -179,6 +185,10 @@ static void __init mpc85xx_mds_setup_arch(void)
|
|||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -227,6 +237,13 @@ static void __init mpc85xx_mds_setup_arch(void)
|
|||
iounmap(bcsr_regs);
|
||||
}
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (lmb_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_pci_dma_ops);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -281,6 +298,9 @@ static int __init mpc85xx_publish_devices(void)
|
|||
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
|
||||
machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
|
||||
|
||||
machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
|
||||
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
|
||||
|
||||
static void __init mpc85xx_mds_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
|
|
|
|||
282
arch/powerpc/platforms/85xx/xes_mpc85xx.c
Normal file
282
arch/powerpc/platforms/85xx/xes_mpc85xx.c
Normal file
|
|
@ -0,0 +1,282 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
|
||||
*
|
||||
* X-ES board-specific functionality
|
||||
*
|
||||
* Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Nate Case <ncase@xes-inc.com>
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
/* A few bit definitions needed for fixups on some boards */
|
||||
#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
|
||||
#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
|
||||
#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
|
||||
|
||||
void __init xes_mpc85xx_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
struct resource r;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_node_by_type(NULL, "open-pic");
|
||||
if (np == NULL) {
|
||||
printk(KERN_ERR "Could not find open-pic node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, &r)) {
|
||||
printk(KERN_ERR "Failed to map mpic register space\n");
|
||||
of_node_put(np);
|
||||
return;
|
||||
}
|
||||
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
MPIC_PRIMARY | MPIC_WANTS_RESET |
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
|
||||
0, 256, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
of_node_put(np);
|
||||
|
||||
mpic_init(mpic);
|
||||
}
|
||||
|
||||
static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
|
||||
{
|
||||
volatile uint32_t ctl, tmp;
|
||||
|
||||
asm volatile("msync; isync");
|
||||
tmp = in_be32(l2_base);
|
||||
|
||||
/*
|
||||
* xMon may have enabled part of L2 as SRAM, so we need to set it
|
||||
* up for all cache mode just to be safe.
|
||||
*/
|
||||
printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
|
||||
|
||||
ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
|
||||
if (machine_is_compatible("MPC8540") ||
|
||||
machine_is_compatible("MPC8560"))
|
||||
/*
|
||||
* Assume L2 SRAM is used fully for cache, so set
|
||||
* L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
|
||||
*/
|
||||
ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
|
||||
|
||||
asm volatile("msync; isync");
|
||||
out_be32(l2_base, ctl);
|
||||
asm volatile("msync; isync");
|
||||
}
|
||||
|
||||
static void xes_mpc85xx_fixups(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int err;
|
||||
|
||||
/*
|
||||
* Legacy xMon firmware on some X-ES boards does not enable L2
|
||||
* as cache. We must ensure that they get enabled here.
|
||||
*/
|
||||
for_each_node_by_name(np, "l2-cache-controller") {
|
||||
struct resource r[2];
|
||||
void __iomem *l2_base;
|
||||
|
||||
/* Only MPC8548, MPC8540, and MPC8560 boards are affected */
|
||||
if (!of_device_is_compatible(np,
|
||||
"fsl,mpc8548-l2-cache-controller") &&
|
||||
!of_device_is_compatible(np,
|
||||
"fsl,mpc8540-l2-cache-controller") &&
|
||||
!of_device_is_compatible(np,
|
||||
"fsl,mpc8560-l2-cache-controller"))
|
||||
continue;
|
||||
|
||||
err = of_address_to_resource(np, 0, &r[0]);
|
||||
if (err) {
|
||||
printk(KERN_WARNING "xes_mpc85xx: Could not get "
|
||||
"resource for device tree node '%s'",
|
||||
np->full_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
|
||||
|
||||
xes_mpc85xx_configure_l2(l2_base);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int primary_phb_addr;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
extern void __init mpc85xx_smp_init(void);
|
||||
#endif
|
||||
static void __init xes_mpc85xx_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
#endif
|
||||
struct device_node *root;
|
||||
const char *model = "Unknown";
|
||||
|
||||
root = of_find_node_by_path("/");
|
||||
if (root == NULL)
|
||||
return;
|
||||
|
||||
model = of_get_property(root, "model", NULL);
|
||||
|
||||
printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
|
||||
model + strlen("xes,"));
|
||||
|
||||
xes_mpc85xx_fixups();
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_node_by_type(np, "pci") {
|
||||
if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
|
||||
of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
|
||||
struct resource rsrc;
|
||||
of_address_to_resource(np, 0, &rsrc);
|
||||
if ((rsrc.start & 0xfffff) == primary_phb_addr)
|
||||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc85xx_smp_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata xes_mpc85xx_ids[] = {
|
||||
{ .type = "soc", },
|
||||
{ .compatible = "soc", },
|
||||
{ .compatible = "simple-bus", },
|
||||
{ .compatible = "gianfar", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init xes_mpc85xx_publish_devices(void)
|
||||
{
|
||||
return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
|
||||
}
|
||||
machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
|
||||
machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
|
||||
machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init xes_mpc8572_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
|
||||
#ifdef CONFIG_PCI
|
||||
primary_phb_addr = 0x8000;
|
||||
#endif
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init xes_mpc8548_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
|
||||
#ifdef CONFIG_PCI
|
||||
primary_phb_addr = 0xb000;
|
||||
#endif
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init xes_mpc8540_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
|
||||
#ifdef CONFIG_PCI
|
||||
primary_phb_addr = 0xb000;
|
||||
#endif
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
define_machine(xes_mpc8572) {
|
||||
.name = "X-ES MPC8572",
|
||||
.probe = xes_mpc8572_probe,
|
||||
.setup_arch = xes_mpc85xx_setup_arch,
|
||||
.init_IRQ = xes_mpc85xx_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
||||
define_machine(xes_mpc8548) {
|
||||
.name = "X-ES MPC8548",
|
||||
.probe = xes_mpc8548_probe,
|
||||
.setup_arch = xes_mpc85xx_setup_arch,
|
||||
.init_IRQ = xes_mpc85xx_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
||||
define_machine(xes_mpc8540) {
|
||||
.name = "X-ES MPC8540",
|
||||
.probe = xes_mpc8540_probe,
|
||||
.setup_arch = xes_mpc85xx_setup_arch,
|
||||
.init_IRQ = xes_mpc85xx_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
|
@ -15,6 +15,7 @@ config MPC8641_HPCN
|
|||
select DEFAULT_UIMAGE
|
||||
select FSL_ULI1575
|
||||
select HAS_RAPIDIO
|
||||
select SWIOTLB
|
||||
help
|
||||
This option enables support for the MPC8641 HPCN board.
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/lmb.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
|
|
@ -27,6 +28,7 @@
|
|||
#include <asm/prom.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/swiotlb.h>
|
||||
|
||||
#include <asm/mpic.h>
|
||||
|
||||
|
|
@ -70,7 +72,9 @@ mpc86xx_hpcn_setup_arch(void)
|
|||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
|
||||
|
|
@ -83,6 +87,9 @@ mpc86xx_hpcn_setup_arch(void)
|
|||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
|
||||
ppc_md.pci_exclude_device = mpc86xx_exclude_device;
|
||||
|
|
@ -94,6 +101,13 @@ mpc86xx_hpcn_setup_arch(void)
|
|||
#ifdef CONFIG_SMP
|
||||
mpc86xx_smp_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (lmb_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_pci_dma_ops);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -158,6 +172,7 @@ static int __init declare_of_platform_devices(void)
|
|||
return 0;
|
||||
}
|
||||
machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices);
|
||||
machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier);
|
||||
|
||||
define_machine(mpc86xx_hpcn) {
|
||||
.name = "MPC86xx HPCN",
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ choice
|
|||
|
||||
If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
|
||||
|
||||
config PPC_BOOK3S
|
||||
config PPC_BOOK3S_32
|
||||
bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
|
||||
select PPC_FPU
|
||||
|
||||
|
|
@ -57,11 +57,14 @@ config E200
|
|||
|
||||
endchoice
|
||||
|
||||
config PPC_BOOK3S
|
||||
default y
|
||||
config PPC_BOOK3S_64
|
||||
def_bool y
|
||||
depends on PPC64
|
||||
select PPC_FPU
|
||||
|
||||
config PPC_BOOK3S
|
||||
def_bool y
|
||||
depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
|
||||
|
||||
config POWER4_ONLY
|
||||
bool "Optimize for POWER4"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o
|
||||
|
||||
obj-$(CONFIG_PPC_PMAC) += powermac/
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
EXTRA_CFLAGS += -mno-minimal-toc
|
||||
endif
|
||||
|
|
@ -48,6 +50,9 @@ obj-$(CONFIG_PPC_DCR) += dcr.o
|
|||
obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o
|
||||
obj-$(CONFIG_UCODE_PATCH) += micropatch.o
|
||||
|
||||
obj-$(CONFIG_PPC_MPC512x) += mpc5xxx_clocks.o
|
||||
obj-$(CONFIG_PPC_MPC52xx) += mpc5xxx_clocks.o
|
||||
|
||||
ifeq ($(CONFIG_SUSPEND),y)
|
||||
obj-$(CONFIG_6xx) += 6xx-suspend.o
|
||||
endif
|
||||
|
|
|
|||
33
arch/powerpc/sysdev/mpc5xxx_clocks.c
Normal file
33
arch/powerpc/sysdev/mpc5xxx_clocks.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/**
|
||||
* mpc5xxx_get_bus_frequency - Find the bus frequency for a device
|
||||
* @node: device node
|
||||
*
|
||||
* Returns bus frequency (IPS on MPC512x, IPB on MPC52xx),
|
||||
* or 0 if the bus frequency cannot be found.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
unsigned int
|
||||
mpc5xxx_get_bus_frequency(struct device_node *node)
|
||||
{
|
||||
struct device_node *np;
|
||||
const unsigned int *p_bus_freq = NULL;
|
||||
|
||||
of_node_get(node);
|
||||
while (node) {
|
||||
p_bus_freq = of_get_property(node, "bus-frequency", NULL);
|
||||
if (p_bus_freq)
|
||||
break;
|
||||
|
||||
np = of_get_parent(node);
|
||||
of_node_put(node);
|
||||
node = np;
|
||||
}
|
||||
if (node)
|
||||
of_node_put(node);
|
||||
|
||||
return p_bus_freq ? *p_bus_freq : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(mpc5xxx_get_bus_frequency);
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
# Makefile for xmon
|
||||
|
||||
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
|
||||
|
||||
ifdef CONFIG_PPC64
|
||||
EXTRA_CFLAGS += -mno-minimal-toc
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
|
|||
struct bcom_task *dmatsk = NULL;
|
||||
|
||||
/* Get ipb frequency */
|
||||
ipb_freq = mpc52xx_find_ipb_freq(op->node);
|
||||
ipb_freq = mpc5xxx_get_bus_frequency(op->node);
|
||||
if (!ipb_freq) {
|
||||
dev_err(&op->dev, "could not determine IPB bus frequency\n");
|
||||
return -ENODEV;
|
||||
|
|
|
|||
|
|
@ -241,7 +241,7 @@ static int __devexit hvc_vio_remove(struct vio_dev *vdev)
|
|||
static struct vio_driver hvc_vio_driver = {
|
||||
.id_table = hvc_driver_table,
|
||||
.probe = hvc_vio_probe,
|
||||
.remove = hvc_vio_remove,
|
||||
.remove = __devexit_p(hvc_vio_remove),
|
||||
.driver = {
|
||||
.name = hvc_driver_name,
|
||||
.owner = THIS_MODULE,
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ static int __devexit hvc_vio_remove(struct vio_dev *vdev)
|
|||
static struct vio_driver hvc_vio_driver = {
|
||||
.id_table = hvc_driver_table,
|
||||
.probe = hvc_vio_probe,
|
||||
.remove = hvc_vio_remove,
|
||||
.remove = __devexit_p(hvc_vio_remove),
|
||||
.driver = {
|
||||
.name = hvc_driver_name,
|
||||
.owner = THIS_MODULE,
|
||||
|
|
|
|||
|
|
@ -868,7 +868,7 @@ static int __devexit hvcs_remove(struct vio_dev *dev)
|
|||
static struct vio_driver hvcs_vio_driver = {
|
||||
.id_table = hvcs_driver_table,
|
||||
.probe = hvcs_probe,
|
||||
.remove = hvcs_remove,
|
||||
.remove = __devexit_p(hvcs_remove),
|
||||
.driver = {
|
||||
.name = hvcs_driver_name,
|
||||
.owner = THIS_MODULE,
|
||||
|
|
|
|||
|
|
@ -197,7 +197,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
|
|||
return -EINVAL;
|
||||
|
||||
/* Determine divider value */
|
||||
divider = mpc52xx_find_ipb_freq(node) / clock;
|
||||
divider = mpc5xxx_get_bus_frequency(node) / clock;
|
||||
|
||||
/*
|
||||
* We want to choose an FDR/DFSR that generates an I2C bus speed that
|
||||
|
|
|
|||
|
|
@ -948,7 +948,7 @@ mpc52xx_fec_probe(struct of_device *op, const struct of_device_id *match)
|
|||
/* Start with safe defaults for link connection */
|
||||
priv->speed = 100;
|
||||
priv->duplex = DUPLEX_HALF;
|
||||
priv->mdio_speed = ((mpc52xx_find_ipb_freq(op->node) >> 20) / 5) << 1;
|
||||
priv->mdio_speed = ((mpc5xxx_get_bus_frequency(op->node) >> 20) / 5) << 1;
|
||||
|
||||
/* The current speed preconfigures the speed of the MII link */
|
||||
prop = of_get_property(op->node, "current-speed", &prop_size);
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ static int mpc52xx_fec_mdio_probe(struct of_device *of,
|
|||
|
||||
/* set MII speed */
|
||||
out_be32(&priv->regs->mii_speed,
|
||||
((mpc52xx_find_ipb_freq(of->node) >> 20) / 5) << 1);
|
||||
((mpc5xxx_get_bus_frequency(of->node) >> 20) / 5) << 1);
|
||||
|
||||
err = of_mdiobus_register(bus, np);
|
||||
if (err)
|
||||
|
|
|
|||
|
|
@ -214,9 +214,10 @@ static void gelic_card_free_chain(struct gelic_card *card,
|
|||
*
|
||||
* returns 0 on success, <0 on failure
|
||||
*/
|
||||
static int gelic_card_init_chain(struct gelic_card *card,
|
||||
struct gelic_descr_chain *chain,
|
||||
struct gelic_descr *start_descr, int no)
|
||||
static int __devinit gelic_card_init_chain(struct gelic_card *card,
|
||||
struct gelic_descr_chain *chain,
|
||||
struct gelic_descr *start_descr,
|
||||
int no)
|
||||
{
|
||||
int i;
|
||||
struct gelic_descr *descr;
|
||||
|
|
@ -407,7 +408,7 @@ static int gelic_card_fill_rx_chain(struct gelic_card *card)
|
|||
*
|
||||
* returns 0 on success, < 0 on failure
|
||||
*/
|
||||
static int gelic_card_alloc_rx_skbs(struct gelic_card *card)
|
||||
static int __devinit gelic_card_alloc_rx_skbs(struct gelic_card *card)
|
||||
{
|
||||
struct gelic_descr_chain *chain;
|
||||
int ret;
|
||||
|
|
@ -1422,8 +1423,8 @@ static const struct net_device_ops gelic_netdevice_ops = {
|
|||
*
|
||||
* fills out function pointers in the net_device structure
|
||||
*/
|
||||
static void gelic_ether_setup_netdev_ops(struct net_device *netdev,
|
||||
struct napi_struct *napi)
|
||||
static void __devinit gelic_ether_setup_netdev_ops(struct net_device *netdev,
|
||||
struct napi_struct *napi)
|
||||
{
|
||||
netdev->watchdog_timeo = GELIC_NET_WATCHDOG_TIMEOUT;
|
||||
/* NAPI */
|
||||
|
|
@ -1443,7 +1444,8 @@ static void gelic_ether_setup_netdev_ops(struct net_device *netdev,
|
|||
* gelic_ether_setup_netdev initializes the net_device structure
|
||||
* and register it.
|
||||
**/
|
||||
int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card)
|
||||
int __devinit gelic_net_setup_netdev(struct net_device *netdev,
|
||||
struct gelic_card *card)
|
||||
{
|
||||
int status;
|
||||
u64 v1, v2;
|
||||
|
|
@ -1491,7 +1493,7 @@ int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card)
|
|||
* the card and net_device structures are linked to each other
|
||||
*/
|
||||
#define GELIC_ALIGN (32)
|
||||
static struct gelic_card *gelic_alloc_card_net(struct net_device **netdev)
|
||||
static struct gelic_card * __devinit gelic_alloc_card_net(struct net_device **netdev)
|
||||
{
|
||||
struct gelic_card *card;
|
||||
struct gelic_port *port;
|
||||
|
|
@ -1542,7 +1544,7 @@ static struct gelic_card *gelic_alloc_card_net(struct net_device **netdev)
|
|||
return card;
|
||||
}
|
||||
|
||||
static void gelic_card_get_vlan_info(struct gelic_card *card)
|
||||
static void __devinit gelic_card_get_vlan_info(struct gelic_card *card)
|
||||
{
|
||||
u64 v1, v2;
|
||||
int status;
|
||||
|
|
@ -1616,7 +1618,7 @@ static void gelic_card_get_vlan_info(struct gelic_card *card)
|
|||
/**
|
||||
* ps3_gelic_driver_probe - add a device to the control of this driver
|
||||
*/
|
||||
static int ps3_gelic_driver_probe(struct ps3_system_bus_device *dev)
|
||||
static int __devinit ps3_gelic_driver_probe(struct ps3_system_bus_device *dev)
|
||||
{
|
||||
struct gelic_card *card;
|
||||
struct net_device *netdev;
|
||||
|
|
|
|||
|
|
@ -2442,7 +2442,7 @@ static const struct iw_handler_def gelic_wl_wext_handler_def = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct net_device *gelic_wl_alloc(struct gelic_card *card)
|
||||
static struct net_device * __devinit gelic_wl_alloc(struct gelic_card *card)
|
||||
{
|
||||
struct net_device *netdev;
|
||||
struct gelic_port *port;
|
||||
|
|
@ -2722,7 +2722,7 @@ static struct ethtool_ops gelic_wl_ethtool_ops = {
|
|||
.set_rx_csum = gelic_net_set_rx_csum,
|
||||
};
|
||||
|
||||
static void gelic_wl_setup_netdev_ops(struct net_device *netdev)
|
||||
static void __devinit gelic_wl_setup_netdev_ops(struct net_device *netdev)
|
||||
{
|
||||
struct gelic_wl_info *wl;
|
||||
wl = port_wl(netdev_priv(netdev));
|
||||
|
|
@ -2738,7 +2738,7 @@ static void gelic_wl_setup_netdev_ops(struct net_device *netdev)
|
|||
/*
|
||||
* driver probe/remove
|
||||
*/
|
||||
int gelic_wl_driver_probe(struct gelic_card *card)
|
||||
int __devinit gelic_wl_driver_probe(struct gelic_card *card)
|
||||
{
|
||||
int ret;
|
||||
struct net_device *netdev;
|
||||
|
|
|
|||
|
|
@ -263,15 +263,21 @@ static void rio_route_set_ops(struct rio_dev *rdev)
|
|||
* device to the RIO device list. Creates the generic sysfs nodes
|
||||
* for an RIO device.
|
||||
*/
|
||||
static void __devinit rio_add_device(struct rio_dev *rdev)
|
||||
static int __devinit rio_add_device(struct rio_dev *rdev)
|
||||
{
|
||||
device_add(&rdev->dev);
|
||||
int err;
|
||||
|
||||
err = device_add(&rdev->dev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
spin_lock(&rio_global_list_lock);
|
||||
list_add_tail(&rdev->global_list, &rio_devices);
|
||||
spin_unlock(&rio_global_list_lock);
|
||||
|
||||
rio_create_sysfs_dev_files(rdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -294,13 +300,14 @@ static struct rio_dev __devinit *rio_setup_device(struct rio_net *net,
|
|||
struct rio_mport *port, u16 destid,
|
||||
u8 hopcount, int do_enum)
|
||||
{
|
||||
int ret = 0;
|
||||
struct rio_dev *rdev;
|
||||
struct rio_switch *rswitch;
|
||||
struct rio_switch *rswitch = NULL;
|
||||
int result, rdid;
|
||||
|
||||
rdev = kzalloc(sizeof(struct rio_dev), GFP_KERNEL);
|
||||
if (!rdev)
|
||||
goto out;
|
||||
return NULL;
|
||||
|
||||
rdev->net = net;
|
||||
rio_mport_read_config_32(port, destid, hopcount, RIO_DEV_ID_CAR,
|
||||
|
|
@ -343,23 +350,16 @@ static struct rio_dev __devinit *rio_setup_device(struct rio_net *net,
|
|||
rio_mport_read_config_32(port, destid, hopcount,
|
||||
RIO_SWP_INFO_CAR, &rdev->swpinfo);
|
||||
rswitch = kmalloc(sizeof(struct rio_switch), GFP_KERNEL);
|
||||
if (!rswitch) {
|
||||
kfree(rdev);
|
||||
rdev = NULL;
|
||||
goto out;
|
||||
}
|
||||
if (!rswitch)
|
||||
goto cleanup;
|
||||
rswitch->switchid = next_switchid;
|
||||
rswitch->hopcount = hopcount;
|
||||
rswitch->destid = destid;
|
||||
rswitch->route_table = kzalloc(sizeof(u8)*
|
||||
RIO_MAX_ROUTE_ENTRIES(port->sys_size),
|
||||
GFP_KERNEL);
|
||||
if (!rswitch->route_table) {
|
||||
kfree(rdev);
|
||||
rdev = NULL;
|
||||
kfree(rswitch);
|
||||
goto out;
|
||||
}
|
||||
if (!rswitch->route_table)
|
||||
goto cleanup;
|
||||
/* Initialize switch route table */
|
||||
for (rdid = 0; rdid < RIO_MAX_ROUTE_ENTRIES(port->sys_size);
|
||||
rdid++)
|
||||
|
|
@ -390,10 +390,19 @@ static struct rio_dev __devinit *rio_setup_device(struct rio_net *net,
|
|||
rio_init_dbell_res(&rdev->riores[RIO_DOORBELL_RESOURCE],
|
||||
0, 0xffff);
|
||||
|
||||
rio_add_device(rdev);
|
||||
ret = rio_add_device(rdev);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
|
||||
out:
|
||||
return rdev;
|
||||
|
||||
cleanup:
|
||||
if (rswitch) {
|
||||
kfree(rswitch->route_table);
|
||||
kfree(rswitch);
|
||||
}
|
||||
kfree(rdev);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -214,9 +214,11 @@ static struct bin_attribute rio_config_attr = {
|
|||
*/
|
||||
int rio_create_sysfs_dev_files(struct rio_dev *rdev)
|
||||
{
|
||||
sysfs_create_bin_file(&rdev->dev.kobj, &rio_config_attr);
|
||||
int err = 0;
|
||||
|
||||
return 0;
|
||||
err = sysfs_create_bin_file(&rdev->dev.kobj, &rio_config_attr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@ static irqreturn_t ps3rom_interrupt(int irq, void *data)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
host = dev->sbd.core.driver_data;
|
||||
host = ps3_system_bus_get_drvdata(&dev->sbd);
|
||||
priv = shost_priv(host);
|
||||
cmd = priv->curr_cmd;
|
||||
|
||||
|
|
@ -387,7 +387,7 @@ static int __devinit ps3rom_probe(struct ps3_system_bus_device *_dev)
|
|||
}
|
||||
|
||||
priv = shost_priv(host);
|
||||
dev->sbd.core.driver_data = host;
|
||||
ps3_system_bus_set_drvdata(&dev->sbd, host);
|
||||
priv->dev = dev;
|
||||
|
||||
/* One device/LUN per SCSI bus */
|
||||
|
|
@ -407,7 +407,7 @@ static int __devinit ps3rom_probe(struct ps3_system_bus_device *_dev)
|
|||
|
||||
fail_host_put:
|
||||
scsi_host_put(host);
|
||||
dev->sbd.core.driver_data = NULL;
|
||||
ps3_system_bus_set_drvdata(&dev->sbd, NULL);
|
||||
fail_teardown:
|
||||
ps3stor_teardown(dev);
|
||||
fail_free_bounce:
|
||||
|
|
@ -418,12 +418,12 @@ static int __devinit ps3rom_probe(struct ps3_system_bus_device *_dev)
|
|||
static int ps3rom_remove(struct ps3_system_bus_device *_dev)
|
||||
{
|
||||
struct ps3_storage_device *dev = to_ps3_storage_device(&_dev->core);
|
||||
struct Scsi_Host *host = dev->sbd.core.driver_data;
|
||||
struct Scsi_Host *host = ps3_system_bus_get_drvdata(&dev->sbd);
|
||||
|
||||
scsi_remove_host(host);
|
||||
ps3stor_teardown(dev);
|
||||
scsi_host_put(host);
|
||||
dev->sbd.core.driver_data = NULL;
|
||||
ps3_system_bus_set_drvdata(&dev->sbd, NULL);
|
||||
kfree(dev->bounce_buf);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,7 +76,6 @@
|
|||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mpc52xx.h>
|
||||
#include <asm/mpc512x.h>
|
||||
#include <asm/mpc52xx_psc.h>
|
||||
|
||||
#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
|
||||
|
|
@ -254,7 +253,7 @@ static unsigned long mpc52xx_getuartclk(void *p)
|
|||
* but the generic serial code assumes 16
|
||||
* so return ipb freq / 2
|
||||
*/
|
||||
return mpc52xx_find_ipb_freq(p) / 2;
|
||||
return mpc5xxx_get_bus_frequency(p) / 2;
|
||||
}
|
||||
|
||||
static struct psc_ops mpc52xx_psc_ops = {
|
||||
|
|
@ -391,7 +390,7 @@ static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
|
|||
|
||||
static unsigned long mpc512x_getuartclk(void *p)
|
||||
{
|
||||
return mpc512x_find_ips_freq(p);
|
||||
return mpc5xxx_get_bus_frequency(p);
|
||||
}
|
||||
|
||||
static struct psc_ops mpc512x_psc_ops = {
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static int __devinit of_platform_serial_setup(struct of_device *ofdev,
|
|||
port->type = type;
|
||||
port->uartclk = *clk;
|
||||
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
|
||||
| UPF_FIXED_PORT;
|
||||
| UPF_FIXED_PORT | UPF_FIXED_TYPE;
|
||||
port->dev = &ofdev->dev;
|
||||
/* If current-speed was set, then try not to change it. */
|
||||
if (spd)
|
||||
|
|
|
|||
|
|
@ -681,22 +681,27 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
|
|||
out_be16(&uccup->rccm, 0xc0ff);
|
||||
|
||||
/* Configure the GUMR registers for UART */
|
||||
if (soft_uart)
|
||||
if (soft_uart) {
|
||||
/* Soft-UART requires a 1X multiplier for TX */
|
||||
clrsetbits_be32(&uccp->gumr_l,
|
||||
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
|
||||
UCC_SLOW_GUMR_L_RDCR_MASK,
|
||||
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
|
||||
UCC_SLOW_GUMR_L_RDCR_16);
|
||||
else
|
||||
|
||||
clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
|
||||
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
|
||||
} else {
|
||||
clrsetbits_be32(&uccp->gumr_l,
|
||||
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
|
||||
UCC_SLOW_GUMR_L_RDCR_MASK,
|
||||
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
|
||||
UCC_SLOW_GUMR_L_RDCR_16);
|
||||
|
||||
clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
|
||||
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
|
||||
clrsetbits_be32(&uccp->gumr_h,
|
||||
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
|
||||
UCC_SLOW_GUMR_H_RFW);
|
||||
}
|
||||
|
||||
#ifdef LOOPBACK
|
||||
clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
|
||||
|
|
@ -706,7 +711,7 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
|
|||
UCC_SLOW_GUMR_H_CDS);
|
||||
#endif
|
||||
|
||||
/* Enable rx interrupts and clear all pending events. */
|
||||
/* Disable rx interrupts and clear all pending events. */
|
||||
out_be16(&uccp->uccm, 0);
|
||||
out_be16(&uccp->ucce, 0xffff);
|
||||
out_be16(&uccp->udsr, 0x7e7e);
|
||||
|
|
@ -765,6 +770,10 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
|
|||
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
|
||||
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
|
||||
QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
||||
} else {
|
||||
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
|
||||
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
|
||||
QE_CR_PROTOCOL_UART, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static const struct hc_driver ps3_ehci_hc_driver = {
|
|||
.port_handed_over = ehci_port_handed_over,
|
||||
};
|
||||
|
||||
static int ps3_ehci_probe(struct ps3_system_bus_device *dev)
|
||||
static int __devinit ps3_ehci_probe(struct ps3_system_bus_device *dev)
|
||||
{
|
||||
int result;
|
||||
struct usb_hcd *hcd;
|
||||
|
|
@ -225,7 +225,7 @@ static int ps3_ehci_remove(struct ps3_system_bus_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ps3_ehci_driver_register(struct ps3_system_bus_driver *drv)
|
||||
static int __init ps3_ehci_driver_register(struct ps3_system_bus_driver *drv)
|
||||
{
|
||||
return firmware_has_feature(FW_FEATURE_PS3_LV1)
|
||||
? ps3_system_bus_driver_register(drv)
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ static const struct hc_driver ps3_ohci_hc_driver = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static int ps3_ohci_probe(struct ps3_system_bus_device *dev)
|
||||
static int __devinit ps3_ohci_probe(struct ps3_system_bus_device *dev)
|
||||
{
|
||||
int result;
|
||||
struct usb_hcd *hcd;
|
||||
|
|
@ -224,7 +224,7 @@ static int ps3_ohci_remove(struct ps3_system_bus_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ps3_ohci_driver_register(struct ps3_system_bus_driver *drv)
|
||||
static int __init ps3_ohci_driver_register(struct ps3_system_bus_driver *drv)
|
||||
{
|
||||
return firmware_has_feature(FW_FEATURE_PS3_LV1)
|
||||
? ps3_system_bus_driver_register(drv)
|
||||
|
|
|
|||
|
|
@ -124,7 +124,6 @@ struct xilinxfb_drvdata {
|
|||
registers */
|
||||
|
||||
dcr_host_t dcr_host;
|
||||
unsigned int dcr_start;
|
||||
unsigned int dcr_len;
|
||||
|
||||
void *fb_virt; /* virt. address of the frame buffer */
|
||||
|
|
@ -325,8 +324,8 @@ static int xilinxfb_assign(struct device *dev,
|
|||
drvdata->regs);
|
||||
}
|
||||
/* Put a banner in the log (for DEBUG) */
|
||||
dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n",
|
||||
(void *)drvdata->fb_phys, drvdata->fb_virt, fbsize);
|
||||
dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
|
||||
(unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
|
||||
|
||||
return 0; /* success */
|
||||
|
||||
|
|
@ -404,9 +403,7 @@ xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
|
|||
u32 tft_access;
|
||||
struct xilinxfb_platform_data pdata;
|
||||
struct resource res;
|
||||
int size, rc;
|
||||
int start = 0, len = 0;
|
||||
dcr_host_t dcr_host;
|
||||
int size, rc, start;
|
||||
struct xilinxfb_drvdata *drvdata;
|
||||
|
||||
/* Copy with the default pdata (not a ptr reference!) */
|
||||
|
|
@ -414,35 +411,39 @@ xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
|
|||
|
||||
dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
|
||||
|
||||
/* Allocate the driver data region */
|
||||
drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata) {
|
||||
dev_err(&op->dev, "Couldn't allocate device private record\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*
|
||||
* To check whether the core is connected directly to DCR or PLB
|
||||
* interface and initialize the tft_access accordingly.
|
||||
*/
|
||||
p = (u32 *)of_get_property(op->node, "xlnx,dcr-splb-slave-if", NULL);
|
||||
|
||||
if (p)
|
||||
tft_access = *p;
|
||||
else
|
||||
tft_access = 0; /* For backward compatibility */
|
||||
tft_access = p ? *p : 0;
|
||||
|
||||
/*
|
||||
* Fill the resource structure if its direct PLB interface
|
||||
* otherwise fill the dcr_host structure.
|
||||
*/
|
||||
if (tft_access) {
|
||||
drvdata->flags |= PLB_ACCESS_FLAG;
|
||||
rc = of_address_to_resource(op->node, 0, &res);
|
||||
if (rc) {
|
||||
dev_err(&op->dev, "invalid address\n");
|
||||
return -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
} else {
|
||||
res.start = 0;
|
||||
start = dcr_resource_start(op->node, 0);
|
||||
len = dcr_resource_len(op->node, 0);
|
||||
dcr_host = dcr_map(op->node, start, len);
|
||||
if (!DCR_MAP_OK(dcr_host)) {
|
||||
dev_err(&op->dev, "invalid address\n");
|
||||
return -ENODEV;
|
||||
drvdata->dcr_len = dcr_resource_len(op->node, 0);
|
||||
drvdata->dcr_host = dcr_map(op->node, start, drvdata->dcr_len);
|
||||
if (!DCR_MAP_OK(drvdata->dcr_host)) {
|
||||
dev_err(&op->dev, "invalid DCR address\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -467,26 +468,12 @@ xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
|
|||
if (of_find_property(op->node, "rotate-display", NULL))
|
||||
pdata.rotate_screen = 1;
|
||||
|
||||
/* Allocate the driver data region */
|
||||
drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata) {
|
||||
dev_err(&op->dev, "Couldn't allocate device private record\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
dev_set_drvdata(&op->dev, drvdata);
|
||||
return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
|
||||
|
||||
if (tft_access)
|
||||
drvdata->flags |= PLB_ACCESS_FLAG;
|
||||
|
||||
/* Arguments are passed based on the interface */
|
||||
if (drvdata->flags & PLB_ACCESS_FLAG) {
|
||||
return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
|
||||
} else {
|
||||
drvdata->dcr_start = start;
|
||||
drvdata->dcr_len = len;
|
||||
drvdata->dcr_host = dcr_host;
|
||||
return xilinxfb_assign(&op->dev, drvdata, 0, &pdata);
|
||||
}
|
||||
err:
|
||||
kfree(drvdata);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __devexit xilinxfb_of_remove(struct of_device *op)
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static int mpc5200_wdt_probe(struct of_device *op,
|
|||
if (!wdt)
|
||||
return -ENOMEM;
|
||||
|
||||
wdt->ipb_freq = mpc52xx_find_ipb_freq(op->node);
|
||||
wdt->ipb_freq = mpc5xxx_get_bus_frequency(op->node);
|
||||
|
||||
err = of_address_to_resource(op->node, 0, &wdt->mem);
|
||||
if (err)
|
||||
|
|
|
|||
Loading…
Reference in a new issue